본문 바로가기
KERD
논문KCI 등재

인공지능 반도체 및 패키징 기술 동향

Artificial Intelligence Semiconductor and Packaging Technology Trend

정재필|김희주
한국마이크로전자및패키징학회 (The Microelectronics And Packaging Society)|2023.09|마이크로전자 및 패키징학회지 (Jornal of the Microelectronics and Packaging Society)|제30권 제3호|pp. 11-19|DOI doi.org/10.6117/kmeps.2023.30.3.011

1

조회

0

다운로드

8

인용

0

참고문헌

키워드

Artificial Intelligence (AI)Through-Si-Via (TSV)Hybrid bonding2.5-dimensional packagingChiplet
주제분류재료공학

초록

최근 Chat GPT와 같은 인공지능 (Artificial Intelligence, AI) 기술의 급격한 발전에 따라 AI 반도체의 중요성이강조되고 있다. AI 기술은 빅데이터 처리, 딥 러닝, 알고리즘 등의 요구사항으로 인해 대용량 데이터를 빠르게 처리할 수있는 능력을 필요로 한다. 그러나 AI 반도체는 대규모 데이터를 처리하는 과정에서 과도한 전력 소비와 데이터 병목현상문제가 발생한다. 반도체 전공정의 초미세공정이 물리적 한계에 도달함에 따라, AI 반도체의 연산을 위한 최신 패키징 기술이 요구되는 추세이다. 본 고에서는 AI 반도체에 적용가능한 인터포저, TSV, 범핑, Chiplet, 하이브리드 본딩 패키징 기술에 대해서 기술하였다. 이러한 기술들은 AI 반도체의 전력 효율과 연산 속도를 향상시키는데 기여할 것으로 기대된다.

Abstract

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

참고문헌 (45)

  1. WIPO Technology Trends 2019; Artificial Intelligence, "WIPO", 40~ (2020)
  2. S. M. Viswanathan, "AI Chips : New Semiconductor Era", International Journal of Advanced Research in Science", Engineering and Technology, 7(8), pp.14687~14694 (2020)
  3. C. H. Yu, "High Performance, High Density RDL for Advanced Packaging", IEEE 68th Electronic Components and Technology Conference (ECTC), pp.587~593 (2018)
  4. G. Shan, "Architecture of computing system based on chiplet", Micromachines, 13(2), pp.105~ (2022)
  5. gpus for deep learning workloads, "Performance of cpus", pp.2018, A. Kayid
  6. B. Li, "Artificial Intelligence (AI) Chip Technology Review", 2019 International Conference on Machine Learning, Big Data and Business Intelligence (MLBDBI), pp.114~117 (2019)
  7. Y. R. Jeong, "A Real-Time Reconfigurable AI Processor Based on FPGA", 2023 IEEE International Conference on Consumer Electronics (ICCE), pp.1~2 (2023)
  8. L. Yang, "Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks", 2020 57th ACM, 2020, 1~6
  9. S. Dutta, "Addressing Unreliability in Emerging Devices and Non-von Neumann Architectures Using Coded Computing", Proceedings of the IEEE, 108(8), pp.1219~1234 (2020)
  10. H. Kim, "A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory", 2022 19th International SoC Design Conference (ISOCC), pp.127~128 (2022)
  11. H. Jun, "HBM (High Bandwidth Memory) DRAM Technology and Architecture", IEEE International Memory Workshop(IMW), pp.16947916~ (2017)
  12. A. K. Singh, "Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules", International Symposium on Microelectronics, 2019(1), pp.000001~000005 (2019)
  13. D. U. Lee, "22.3 A 128Gb 8-High 512GB", s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST, 2020 (2020), 334~336
  14. K. J. Han, "System Packaging Technology Development Trends", KIEES Magazine : Electromagnetic Technology, 31(1), pp.31~40 (2020)
  15. S. Y. Hou, "Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology", IEEE Transactions on Electron Devices, 64(10), pp.4071~4077 (2017)
  16. R. Chaware, "Assembly Challenges in Developing 3D IC package with Ultra High Yield and High Reliability", 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), pp.1447~1451 (2015)
  17. G. Duan, "Die Embedding Challenges for EMIB Advanced Packaging Technology", 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp.1~7 (2021)
  18. R. Mahajan, "Embedded Multi-Die Interconnect Bridge (EMIB) –A High Density High Bandwidth Packaging Interconnect", 2016 IEEE 66th ECTC Conference, pp.557~565 (2016)
  19. A. C. Durgun, "Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration", 2019IEEE 69th ECTC conference, pp.667~673 (2019)
  20. R. Mahajan, "Embedded Multidie Interconnect Bridge – A Localized, High-Density Multichip Packaging Interconnect", IEEE Transactions on Components, Packaging, and Manufacturing Technology, 9(10), pp.1952~1962 (2019)
  21. B. M. D. Sawyer, "Design and Demonstration of a 2. 5-D Glass Interposer BGA Package for High Bandwidth and Low Cost", IEEE Transactions on Components, Packaging and Manufacturing Technology, 7(4), pp.552~562 (2017)
  22. K.-L. Suk, "Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications", 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), pp.64~69 (2018)
  23. J. Lee, "Amkor's 2.5 D Package and HDFOAdvanced Heterogeneous Packaging Solutions" (2018), China Integrated Circuits
  24. S. C. Hong, "Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microelectronics Reliability, 51(12), pp.2228~2235 (2011)
  25. D. -H. Jung, "Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping", Journal of Materials Engineering and Performance, 24, pp.1107~1115 (2015)
  26. H. C Kim, "Bottom-Up Filling of TSV-Scaled Trenches by Using Step Current Electrodeposition", ECS Electrochemistry Letters, 4(10) (2015)
  27. S. Thangaraju, "Successful void free gap fill of 3μm, high AR via middle, Through Silicon Vias at wafer level", 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014), pp.51~56 (2014)
  28. S. Kim, "Processing-in-memory in High Bandwidth Memory (PIM-HBM) Architecture with Energyefficient and Low Latency Channels for High Bandwidth System", 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp.1~3 (2019)
  29. S. Kim, "Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory(PIM-HBM)Scheme", IEEE Transactions on Components, Packaging and Manufacturing Technology, 11(11), pp.1955~1970 (2021)
  30. S. Kim, "Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM)", 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pp.1~3 (2021)
  31. G. B. Hamad, "Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits", Microelectronics Reliability, 55(1), pp.238~250 (2015)
  32. S. Kumar, "Soft error issue and importance of low alpha solders for microelectronics packaging", Rev. Adv. Mater. Sci, 34, pp.185~202 (2013)
  33. D. Jung, "High Shear Speed Characteristics of Sub-100 μm Low Alpha SAC105Solder Bump Directly Fabricated on Cu Filled Through Si Via for 3D Integration", Journal of Microelectronics and Electronic Packaging, 12(3), pp.161~169 (2015)
  34. J. H. Lau, "Recent Advances and Trends in Advanced Packaging", IEEE Transactions on Components, Packaging and Manufacturing Technology, 12(2), pp.228~252 (2022)
  35. D. Stow, "Cost-effective design of scalable high-performance systems using active and passive interposers", 2017 IEEE, 2017, 1~8
  36. G. H. Loh, "A Research Retrospective on AMD's Exascale Computing Journey", ISCA ’23: Proceedings of the 50th Annual International Symposium on Computer Architecture, 81, pp.1~14 (2023)
  37. R. Swaminathan, "Advanced packaging: Enabling Moore’s Law’s next frontier through heterogeneous integration", IEEE Hot Chip Conference, pp.1~25 (2021)
  38. L. Ji, "Waferto-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages", IEEE Transactions on Components, Packaging and Manufacturing Technology, 10(12), pp.2106~2117 (2020)
  39. M. -H. Roh, "Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging", Metallurgical and Materials Transactions A, 46, pp.2051~2062 (2015)
  40. J. J. Ong, "Low-Temperature Cu", SiO2 Hybrid Bonding with Low Contact Resistance Using(111)-Oriented Cu Surfaces, 2022, pp.15(5), 1888~
  41. M.-F. Chen, "System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration", 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp.594~599 (2019)
  42. W.-L. Chiu, "Low-Temperature Wafer-to-Wafer Hybrid Bonding by Nanocrystalline Copper", 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), pp.679~684 (2022)
  43. M. F. Chen, "SoIC for Low-Temperature, Multi-Layer 3D Memory Integration", 2020IEEE 70th Electronic Components and Technology Conference (ECTC), pp.855~860 (2020)
  44. 서한결, "Cu-SiO2 하이브리드 본딩", 마이크로전자 및 패키징학회지, 27(1), pp.17~24 (2020), 한국마이크로전자및패키징학회
  45. T.-H. Hung, "Investigation of Wet Pretreatment to Improve Cu-Cu Bonding for Hybrid Bonding Applications", 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp.700~705 (2021)

관련 논문AI추천

AI 반도체 패키징을 위한 TGV 및 Cu 충전 연구의 최근 동향선신희, 정재필, 천성경한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2024 · 제31권 제4호차세대 반도체 패키징: 실리콘 포토닉스 기반 Co-packaged Optics의 연구 개발 현황김강석, 김영현, 신석영, 윤석현, 정현지, 정희윤, 조경진, 진태원한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2024 · 제31권 제4호웨이퍼 레벨 패키지 신뢰성 수명 예측을 위한 인공지능 기술 연구동향김광석, 이동근, 정건주한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2025 · 제32권 제1호Advanced Package용 Molded Bridge Die on Substrate(MBoS) 공정 기술 연구고용남, 김동규, 장상규, 장용규, 전재영, 최원석한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2024 · 제31권 제2호저온 Cu 하이브리드 본딩을 위한 폴리머 본딩김지훈, 박종경한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2024 · 제31권 제3호HBM 하이브리드 본딩을 위한 계측 및 검사 최신 기술 동향김영훈, 송일신, 이명호, 이상웅, 이종수, 임은재, 장병록, 장성규, 주승환, 최원영, 편경록, 홍태선한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2025 · 제32권 제4호

이 간행물의 다른 논문 (14건)

첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향윤정원, 이효원, 노은채pp. 1-10Ti3C2Tx MXene 기반 전극 소재의 자가 치유 적용 기술 개발 동향정승부, 최준상, 김종웅pp. 20-34ESG를 위한 반도체 패키지 기술 트렌드서민석pp. 35-39인터포저를 이용한 Stacked PCB의 휨 및 솔더 조인트 강도 연구김기풍, 좌성훈, 황보유환pp. 40-50강유전체 분극 이력곡선의 측정 정밀도 향상박재환pp. 51-55
원문 보기