차세대 반도체 패키징: 실리콘 포토닉스 기반 Co-packaged Optics의 연구 개발 현황
Next-Generation Semiconductor Packaging: Status of Co-Packaged Optics based on Silicon Photonics
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초록
인공지능(AI) 기술의 급속한 발전이 대규모 데이터 처리에 대한 수요를 크게 증가시킴에 따라 반도체 패키징에서 Optical I/O 기술의 중요성이 부각되고 있다. 특히 AI 모델과 고성능 컴퓨팅(HPC) 시스템이 점점 더 복잡해지면서, “Interconnect Wall” 또는 “Power Wall”으로 불리는 인터커넥트 병목현상을 극복하는 것이 더욱 중요해지고 있다. 이러한 병목현상 극복을 위해 Co-Packaged Optics(CPO)가 해결책으로 떠오르고 있으며, 이를 통해 AI 및 HPC 시스템에 필요한 고속 데이터 전송이 이뤄질 것으로 기대되고 있다. 본 논문에서는 거대 AI 모델 연산을 위한 차세대 HPC 컴퓨팅노드의 고속, 저전력, 저지연 네트워크를 위한 실리콘 포토닉스 기반 CPO 기술에 대해 소개하고, 특히, CPO를 기반으로고도화되고 있는 첨단 패키징 분야의 Opto-chiplet(광학칩렛) 패키징 기술에 대한 현황과 향후 전망을 제시해 보고자 한다.
Abstract
The rapid advancement of artificial intelligence (AI) technology has significantly increased the demand for large-scale data processing, highlighting the significant role of Optical I/O technology in semiconductor packaging. As AI models and high-performance computing (HPC) systems continue to grow in complexity, overcoming challenges such as the “Interconnect Wall” or “Power Wall,” which refer to interconnect bottlenecks, has become increasingly crucial. To address these challenges, Co-packaged Optics (CPO) has emerged as a promising solution, designed to enable the highspeed data transmission critical for AI and HPC systems. This paper will present Optical Interconnects, Silicon Photonics, and CPO as essential components for enhancing energy efficiency in next-generation AI and HPC implementations. In this paper, we introduce silicon photonics-based CPO technology for high-speed, low-power, and low-latency networks in next-generation HPC computing nodes designed to handle massive AI model operations. In particular, we examine the latest trends in advanced packaging—including Opto-chiplet packaging—built upon CPO and discuss its current status and future outlook.
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