65 nm CMOS 위상 배열 시스템을 위한 20 dB의 가변 이득 범위를 갖는 조정 캐스코드 가변 이득 증폭기
A Regulated Cascode Variable Gain Amplifier with 20 dB Gain Control Range for Phase Array Systems in 65 nm CMOS
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초록
This paper proposes the current canceling variable gain amplifier (VGA) using a regulated cascode topology that reduces the output phase error between the maximum voltage gain state and the minimum voltage gain state. Since the output phase variation is inversely proportional to the transconductance of the standard gate transistor, the regulated cascode topology can help reduce phase variation and, thus, phase error by increasing the transconductance of the CG transistor. The proposed VGA is implemented in 65 nm CMOS and exhibits 13.8 dB maximum voltage gain, 20 dB voltage control range, 2.9-degree phase error over 25.8 GHz-32.5 GHz 3-dB bandwidth, and 1.28-degree phase error at the center frequency of 29.5 GHz.
Abstract
This paper proposes the current canceling variable gain amplifier (VGA) using a regulated cascode topology that reduces the output phase error between the maximum voltage gain state and the minimum voltage gain state. Since the output phase variation is inversely proportional to the transconductance of the standard gate transistor, the regulated cascode topology can help reduce phase variation and, thus, phase error by increasing the transconductance of the CG transistor. The proposed VGA is implemented in 65 nm CMOS and exhibits 13.8 dB maximum voltage gain, 20 dB voltage control range, 2.9-degree phase error over 25.8 GHz-32.5 GHz 3-dB bandwidth, and 1.28-degree phase error at the center frequency of 29.5 GHz.
참고문헌 (12)
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