Design of K-Band CMOS Variable Gain Amplifier Using Amplification Stage and Variable Attenuation Stage
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In this study, we design a K-band CMOS variable gain amplifier (VGA) for beamforming system applications. The designed VGA consists of amplification and attenuation stages. The amplification stage consists of two common-source gain stages and has a power gain of approximately 18 dB in the simulation. In the case of the attenuation stage, it has a total of 5-bit attenuation steps, and the attenuation range in the simulation is 31 dB. To suppress insertion loss, attenuation bits for low attenuation levels were designed in a distributed structure. On the other hand, attenuation bits for high attenuation levels are designed in a π-structure to secure high attenuation levels. In addition, to suppress the phase error, tail capacitors are added to transistors used in the attenuation stage. The designed K-band VGA was manufactured using a 65-nm RFCMOS process. The chip size of the designed VGA was 0.65 × 0.50 mm2. At operating frequencies 22.0 GHz to 23.6 GHz, the measured variable gain range was between 26.5 dB and 28.2 dB. In this case, the measured RFM phase and attenuation errors were less than 6.40° and 1.24 dB, respectively.
Abstract
In this study, we design a K-band CMOS variable gain amplifier (VGA) for beamforming system applications. The designed VGA consists of amplification and attenuation stages. The amplification stage consists of two common-source gain stages and has a power gain of approximately 18 dB in the simulation. In the case of the attenuation stage, it has a total of 5-bit attenuation steps, and the attenuation range in the simulation is 31 dB. To suppress insertion loss, attenuation bits for low attenuation levels were designed in a distributed structure. On the other hand, attenuation bits for high attenuation levels are designed in a π-structure to secure high attenuation levels. In addition, to suppress the phase error, tail capacitors are added to transistors used in the attenuation stage. The designed K-band VGA was manufactured using a 65-nm RFCMOS process. The chip size of the designed VGA was 0.65 × 0.50 mm2. At operating frequencies 22.0 GHz to 23.6 GHz, the measured variable gain range was between 26.5 dB and 28.2 dB. In this case, the measured RFM phase and attenuation errors were less than 6.40° and 1.24 dB, respectively.
참고문헌 (24)
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