D-band High Gain and Wide Bandwidth Power Amplifier Design in 65nm CMOS Adopting Dual-Peak Gmax Technique
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This paper presents a design of a CMOS D-band high gain and wide bandwidth amplifier adopting the dual-peak Gmax technique. The proposed amplifier applies the dual-frequency Gmax technique based on 3-embedding, which provides high gain over a wide bandwidth. By utilizing the degree of freedom of 3-embedding, we designed a core with optimal input and output impedance. After that, a D-band 3-stage power amplifier is constructed using the designed Gmax-core. When VDD=1V, the measured gain peaks 16.8 dB at 161 GHz with the 3-dB bandwidth of 18.6 GHz and the operating frequency from 150.2 GHz to 168.8 GHz. The maximum output power is 5.65 dBm at 159 GHz and shows performance ranging from 1.39 to 5.65 dBm across the entire operating frequency range. The DC power consumption is 98 mW. The total chip area of the power amplifier is 0.224 mm2.
Abstract
This paper presents a design of a CMOS D-band high gain and wide bandwidth amplifier adopting the dual-peak Gmax technique. The proposed amplifier applies the dual-frequency Gmax technique based on 3-embedding, which provides high gain over a wide bandwidth. By utilizing the degree of freedom of 3-embedding, we designed a core with optimal input and output impedance. After that, a D-band 3-stage power amplifier is constructed using the designed Gmax-core. When VDD=1V, the measured gain peaks 16.8 dB at 161 GHz with the 3-dB bandwidth of 18.6 GHz and the operating frequency from 150.2 GHz to 168.8 GHz. The maximum output power is 5.65 dBm at 159 GHz and shows performance ranging from 1.39 to 5.65 dBm across the entire operating frequency range. The DC power consumption is 98 mW. The total chip area of the power amplifier is 0.224 mm2.
참고문헌 (6)
- H. Bameri, "A High-Gain mm-Wave Amplifier Design : An Analytical Approach to Power Gain Boosting", IEEE Journal of Solid-State Circuits, 52(2), pp.357~370 (2017)
- D. -W. Park, "A 280-", 300-GHz Three-Stage Amplifiers in 65-nm CMOS With 12-, 1. 4% PAE While Dissipating 17. 9 mW, pp.IEEE Microwave and Wireless Components Letters, 2018[DOI]
- D. -W. Park, "A 230–260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak Gmax-Core", IEEE Journal of Solid-State Circuits, 54(6), pp.1613~1623 (2019)
- D. -W. Park, "A D-band power amplifier in 65-nm CMOS by adopting simultaneous output power-and gain-atched Gmax-core", IEEE Access, 9, pp.99 039~99 049 (2021)
- A. Hamani, "A 125.5-157 GHz 8 dB NF and 16 db of gain D-band low noise amplifier in CMOS SOI 45 nm", 2020 IEEE, 2020, 197~200
- D. Simic, "Analysis and design of lossy capacitive over-neutralization technique for amplifiers operating near fmax", IEEE Transactions on Circuits and Systems I : Regular Papers, 68(5), pp.1945~1955 (2021)