DC-DC buck converter using hopping technique and DTMOS Schmitt Trigger logic gates for EMC
2
조회
0
다운로드
0
인용
0
참고문헌
초록
A few circuits for Electromagnetic Compatibility (EMC) were designed through IDEC’s last MPW (MS180-15030) process. One is DC-DC buck converter, and the other is Dynamic Threshold MOSFET (DTMOS) Schmitt Trigger (S. T.) logic gates. In this project, an EMI reduction technique is applied to the DC-DC converter. The frequency hopping technique is applied to reduce the power spectrum of the switching node of DC-DC converter which is the most dominant node generates EMI. The DC-DC converter with hopping frequency techniques is taped-out using 180nm CMOS process. The test results of the chip shows a significant improvement of the voltage spectrum at both output node and switching node of the DC-DC converter. Thus, the EMI generated by DC-DC converter is reduced by applying the frequency hopping technique. Meanwhile, DTMOS S. T. logic gates are designed and fabricated using 180nm CMOS process. Especially, Deep N-well was used to get the separated NMOS body potential. These S. T. gates can be used for low power applications to increase noise immunity of the digital circuit. The proposed gates are verified with a simple example digital circuit.
Abstract
A few circuits for Electromagnetic Compatibility (EMC) were designed through IDEC’s last MPW (MS180-15030) process. One is DC-DC buck converter, and the other is Dynamic Threshold MOSFET (DTMOS) Schmitt Trigger (S. T.) logic gates. In this project, an EMI reduction technique is applied to the DC-DC converter. The frequency hopping technique is applied to reduce the power spectrum of the switching node of DC-DC converter which is the most dominant node generates EMI. The DC-DC converter with hopping frequency techniques is taped-out using 180nm CMOS process. The test results of the chip shows a significant improvement of the voltage spectrum at both output node and switching node of the DC-DC converter. Thus, the EMI generated by DC-DC converter is reduced by applying the frequency hopping technique. Meanwhile, DTMOS S. T. logic gates are designed and fabricated using 180nm CMOS process. Especially, Deep N-well was used to get the separated NMOS body potential. These S. T. gates can be used for low power applications to increase noise immunity of the digital circuit. The proposed gates are verified with a simple example digital circuit.
참고문헌 (4)
- Krishna Mainali, "Conducted EMI Mitigation Techniques for Switch-Mode Power Converters: A Survey", IEEE Transactions on Power Electronics, 25(9) (2010)
- Chengwu Tao, "A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping", IEEE Transactions on Circuits and Systems—II: express briefs, 58(11) (2011)
- K. S. Kim, "Noise-immune Design of Schmitt Trigger Logic Gate using DTMOS for Sub-threshold Circuits", EMC Compo 2013 (2013)
- Zhang, C., "Low voltage CMOS Schmitt trigger circuits", Electronics Letters, 39(24), pp.1696~1698 (2003)