Design of a Current-Controlled Oscillator for Wide-Dynamic-Range, Time-Based, Delta-Sigma Modulator
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This paper presents a design of 15-stage, current-controlled oscillator (CCO) for wide-dynamic-range, time-based, delta-sigma modulator (DSM). The DSM utilizes a time-based quantizer which consists of ring CCO-based integrator and phase extended quantizer. In order to achieve both high loop-gain of the DSM and low-power consumption of the oscillator, the CCO is designed only with inverter delay-cells. In addition, phase extended quantizer is used to add most-significant bit to the DSM output, increasing resolution of the DSM. The designed DSM also utilizes the inherent clocked-averaging property. As a result, the DSM does not need an external dynamic element matching circuit to reduce the effect of the digital-to-analog converter mismatch. The simulation results show that the center frequency and gain of the CCO are near 1.25 MHz and 949 GHz/A under the bias current of 1.2 μA. Through an experiment using the fabricated chip in 65-nm CMOS technology, we confirmed those efficient performances of the designed CCO.
Abstract
This paper presents a design of 15-stage, current-controlled oscillator (CCO) for wide-dynamic-range, time-based, delta-sigma modulator (DSM). The DSM utilizes a time-based quantizer which consists of ring CCO-based integrator and phase extended quantizer. In order to achieve both high loop-gain of the DSM and low-power consumption of the oscillator, the CCO is designed only with inverter delay-cells. In addition, phase extended quantizer is used to add most-significant bit to the DSM output, increasing resolution of the DSM. The designed DSM also utilizes the inherent clocked-averaging property. As a result, the DSM does not need an external dynamic element matching circuit to reduce the effect of the digital-to-analog converter mismatch. The simulation results show that the center frequency and gain of the CCO are near 1.25 MHz and 949 GHz/A under the bias current of 1.2 μA. Through an experiment using the fabricated chip in 65-nm CMOS technology, we confirmed those efficient performances of the designed CCO.
참고문헌 (10)
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