Design of a low power 4th-order delta-sigma modulator with single reconfigurable amplifier
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This paper describes the 4th-order feedback deltasigma modulator with only one amplifier for the application of bio signal processing. The amplifier was reused 4 times by using time interleaving technique. For reducing KT/C noise which most related to integrating capacitance, first and second reused op-amp is designed to load 20pF integrating capacitor and third and fourth is designed to load 1pF and 250fF capacitor each. To solve stability issue made by different capacitance, this paper proposed stage variable op-amp. The modulator was designed with 0.18um CMOS standard process and dissipates the power of 354uW with supply voltage of 1.8V. The measurement results demonstrate the peak SNDR of 72.8dB and the ENOB of 11.8bits with an input signal frequency of 250Hz, a sampling frequency 256kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 128. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.
Abstract
This paper describes the 4th-order feedback deltasigma modulator with only one amplifier for the application of bio signal processing. The amplifier was reused 4 times by using time interleaving technique. For reducing KT/C noise which most related to integrating capacitance, first and second reused op-amp is designed to load 20pF integrating capacitor and third and fourth is designed to load 1pF and 250fF capacitor each. To solve stability issue made by different capacitance, this paper proposed stage variable op-amp. The modulator was designed with 0.18um CMOS standard process and dissipates the power of 354uW with supply voltage of 1.8V. The measurement results demonstrate the peak SNDR of 72.8dB and the ENOB of 11.8bits with an input signal frequency of 250Hz, a sampling frequency 256kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 128. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.
참고문헌 (11)
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