Design of a 12 to 14.5 GHz Digitally-Controlled Oscillator for an Ultra-Low-Jitter PLL

Abstract

A DCO was designed for an ultra-low-jitter digital sub-sampling PLL. To suppress the enormous amount of quantization noise, a very fine frequency resolution is critical. Also, the phase noise of an LC VCO itself is crucial for ultra-low-jitter applications. For high-performance LC VCO design, a basic insight into the oscillator is needed. The proposed DCO consists of a string-type RDAC, MASH 1-1 DSM, and CMOS-type cross-coupled LC VCO. The frequency resolution is significantly increased by using the DSM. The proportional path has a 17-bit resolution, while the integral path has an 18-bit resolution. The DSM operates at 400 MHz, and its quantization noise is canceled by the 2nd-order low-pass filter at the output of the DAC. By adopting 2nd-order noise shaping, the quantization noise at the PLL output is negligible. The DAC was designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has a 12 to 14.5 GHz frequency tuning range. The phase noise at a 1 MHz offset frequency is –109 dBc/Hz at a 14-GHz output. The average power consumption is 5.5 mW. The calculated FOM at a 1-MHz offset frequency is –184.5 dB.