A Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop
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A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with an averaging circuit (AC) and an effectively negative feedback functioned capacitor is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal 0.18μm CMOS process shows 13.4-ps rms jitter.
Abstract
A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with an averaging circuit (AC) and an effectively negative feedback functioned capacitor is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal 0.18μm CMOS process shows 13.4-ps rms jitter.
참고문헌 (12)
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