비아 홀(TSV)의 Cu 충전 및 범핑 공정 단순화
Copper Filling to TSV (Through-Si-Via) and Simplification of Bumping Process
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초록
3차원 Si 칩 패키징 공정을 위한 비아 홀(TSV: Through-Si-Via) 및 Au 시드층 형성, 전기 도금을 이용한 Cu 충전기술과 범핑 공정 단순화에 관하여 연구하였다. 비아 홀 형성을 위하여 SF6 와 C4F8 플라즈마를 교대로 사용하는DRIE(Deep Reactive Ion Etching) 법을 사용하여 Si 웨이퍼를 에칭하였다. 1.92 ks동안 에칭하여 직경 40 μm, 깊이 80 μm 의 비아 홀을 형성하였다. 비아 홀의 옆면에는 열습식 산화법으로 SiO2 절연층을, 스퍼터링 방법으로 Ti 접합층과 Au 시드층을 형성하였다. 펄스 DC 전기도금법에 의해 비아 홀에 Cu를 충전하였으며, 1000 mA/dm2 의 정펄스 전류에서 5 s 동안, 190 mA/dm2 의 역펄스 조건에서 25 s 동안 인가하는 조건으로 총 57.6 ks 동안 전기도금하였다. Si 다이 상의 Cu plugs 위에 리소그라피 공정 없이 전기도금을 실시하여 Sn 범프를 형성할 수 있었으며, 심각한 결함이 없는 범프를 성공적으로 제조할 수 있었다.
Abstract
Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using SF6 and C4F8 plasmas alternately. The vias were 40 μm in diameter, 80 μm in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of SiO2 was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/dm2 for 5 s and a reverse pulse current density of 190 mA/dm2 for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.
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