75mm Cu via가 형성된 3D 스택 패키지용 interconnection 공정 및 접합부의 전기적 특성
Interconnection Process and Electrical Properties of the Interconnection Joints for 3DStack Package with 75mm Cu Via
0
조회
0
다운로드
0
인용
0
참고문헌
초록
직경 75m, 높이 90m 및 150m 피치의 Cu via를 통한 삼차원 배선구조를 갖는 스택 시편을 deep RIE를 이용한 via hole 형성공정, 펄스-역펄스 전기도금법에 의한 Cu via filling 공정, CMP를 이용한 Si thinning 공정, photholithography, 금속박막 스퍼터링, 전기도금법에 의한 Cu/Sn 범프 형성공정 및 플립칩 공정을 이용하여 제작하였다. Cu via를 갖는 daisy chain 시편에서 측정한 접속범프 개수에 따른 daisy chain의 저항 그래프의 기울기로부터 Cu/Sn 범프 접속저항과 Cu via 저항을 구하는 것이 가능하였다. 270oC에서 2분간 유지하여 플립칩 본딩시 100´100m 크기의 Cu/Sn 범프 접속저항은 6.7 m이었으며, 직경 75m, 높이 90m인 Cu via의 저항은 2.3m이었다.
Abstract
Stack specimen with three dimensional interconnection structure through Cu via of 75m diameter, 90m height and 150m pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined from the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip-chip bonded at 270C for 2 minutes, the contact resistance of the Cu/Sn bump joints of 100100m size was 6.7m, and the Cu via resistance of 75m diameter, 90m height was 2.3m.
참고문헌 (18)
- "A review of 3-D packaging technology", packaging and manufacturing technol., pp.212~14 (1988)
- "Three-dimensional interconnect technology for ultra-compact MMICs", 41, pp.1451~1455 (1997)
- "A portable multimedia terminal", 30, pp.64~75 (1992)
- "Aladdin: Packaging lessons learned", pp.7~11 (1995)
- "Three-dimenstional electronics pakcaging", pp.7~11 (1995)
- "Current status of research and development for three-dimensional and chip stack technology", 40, pp.3032~3037 (2001)
- "Three-dimensional integration technology based on wafer bonding technique using micro-bumps", pp.1073~1074 (1995)
- "Three dimensional metallization for vertically integrated circuits", 37, pp.39~47 (1997)
- "Three-dimensional electronics packaging", pp.159~161 (1993)
- "3-D-multichip moudule" (1995)
- "Int. Conf. on High Density Packaging and MCMs", pp.248~253 (1999)
- "3D packaging promises performance, reliability gains with small footprints and lower profiles" (2005)
- "Advanced TAB", BGA multi-chip stacked module for high density LSI packages, 1994, 68~76
- "New film-carrier-assembly technology `transferred bump TAB", pp.122~127 (1986)
- "DC", pulse plating of copper for trench, pp.2001, 114[DOI]
- "Microchip fabrication", pp.39~ (1997), mcgraw hill
- "Effect of bonding stress on the contact resistance of the Sn", Ag bump for chip-on-glass bonding using non-conductive adhesive, 2005, pp.43, 248~254
- "Semiconductor material and device characterization", pp.10~ (1998), John Wiley & Son Inc.,