Design of On-interposer Active Power Distribution Network for an Efficient Simultaneous Switching Noise Suppression in 2.5D/3D IC
0
조회
0
다운로드
0
인용
0
참고문헌
초록
Dynamic voltage frequency scaling (DVFS) and adaptive voltage frequency scaling (AVFS) are primary methods of conserving power in a microprocessor. By these technologies, a simultaneous switching current (SSC) spectrum drawn by integrated circuits (ICs) varies in frequency domain. However, conventional power distribution network (PDN) is impossible to respond the varying SSC spectrum due to its passive characteristics. In this paper, we propose an on-interposer active PDN to efficiently suppress the simultaneous switching noise (SSN) whose frequency is changing. The on-interposer active PDN is a controllable on-interposer decoupling capacitance scheme with external operation based on monitored SSN voltage. The operation of the proposed on-interposer active PDN is verified through simulations in frequency and time domain.
Abstract
Dynamic voltage frequency scaling (DVFS) and adaptive voltage frequency scaling (AVFS) are primary methods of conserving power in a microprocessor. By these technologies, a simultaneous switching current (SSC) spectrum drawn by integrated circuits (ICs) varies in frequency domain. However, conventional power distribution network (PDN) is impossible to respond the varying SSC spectrum due to its passive characteristics. In this paper, we propose an on-interposer active PDN to efficiently suppress the simultaneous switching noise (SSN) whose frequency is changing. The on-interposer active PDN is a controllable on-interposer decoupling capacitance scheme with external operation based on monitored SSN voltage. The operation of the proposed on-interposer active PDN is verified through simulations in frequency and time domain.
참고문헌 (8)
- J. Pak, "Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation", Proc. IEEE Electromagn.Electron.Mater.Packag., pp.1~6 (2007)
- P. G. Emma, "Is 3D Chip Technology the Next Growth Engine for Performance Improvement", IBM J. Res. Develop., 52(6), pp.541~552 (2008)
- K. Kim, "Interposer Power Distribution Network (PDN)Modeling Using a Segmentation Method for 3-D ICs with TSVs", IEEE Trans. Compon.,Packag. Manuf., 3(11), pp.1891~1906 (2013)
- "High Bandwidth Memory (HBM) Dram. JEDEC Standard JESD235A", ~ (2016)
- J. Shim, "An Adaptive On-chip ESR Controller Scheme in Power Distribution Network for Simultaneous Switching Noise Reduction", IEEE Trans. Electrical Performance of Electronic Packaging. (2008)
- Y. Kim, "Measurement and Analysis of Glass Interposer Power Distribution Network Resonance Effects on High-Speed Through Glass Via Channel", IEEE Trans. Electromagnetic Compatibility Society
- A. C. Scogna, "Signal and Power Integrity Analysis of Differential Lines in Multilayer Printed Circuit Boards With Embedded Electromagnetic Bandgap Structures", IEEE Trans. Electromagnetic Compatibility, 2009 IEEE Symposium on., 52(2), pp.357~364 (2010)
- K. Cho, "Signal and Power Integrity Design of 2.5D High Bandwidth Memory Module on Si Interposer", IEEE Trans. Pan Pacific Microelectronics Symposium (2016)