Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network(PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supplynoise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/Ointerfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individualI/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order tohave the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impacton jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise,the on-die noise measurements were measured and results were compared with the original PDN where each I/O andCore PDN are standalone and isolated are used as a benchmark.
Abstract
In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network(PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supplynoise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/Ointerfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individualI/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order tohave the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impacton jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise,the on-die noise measurements were measured and results were compared with the original PDN where each I/O andCore PDN are standalone and isolated are used as a benchmark.
참고문헌 (7)
- M. G. Gericota, "A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs", IEEE Proceedings of Design, Automation and Test, EuropeConference and Exhibition 2002, pp.1126~ (2002)
- S. Molavi, "Concurrent Test Implementations", 16th Asian Test Symposium, 2007, pp.214~ (2007)
- J. Ma, "Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths", 27th IEEE VLSI Test Symposium, VTS ‘09, pp.221~ (2009)
- I. Polian, "Power Droop Testing", International Conference on Computer Design 2006, ICCD 2006, pp.243~ (2007)
- Pan, Y. C, "Mixed Signal validation of the Intel(R) Pentium (R) 4 microprocessor power-up sequence", Electrical Performance of Electronic Packaging, 2003, pp.163~ (2003)
- K. Arabi, "Power noise and its impact on production test and validation of SOC devices", 28th VLSI Test Symposium (VTS), pp.~285 (2010)
- F. N. Tan, "Finding the worst case supply noiseexcitation methodology for high speed I", O interfaces, 2011, 161~