전력전달 및 분배 향상을 위한 Interconnect 공정 기술
Interconnect Process Technology for High Power Delivery and Distribution
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초록
Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.
Abstract
Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.
참고문헌 (32)
- N. H. Khan, "Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies", IEEE Trans. VLSI systems, 19(4), pp.647~ (2011)
- 김사라은경, "3D Wafer Stacking Technology", MRS, pp.29~36 (2002)
- R. Plieninger, "Modern IC packaging trends and their reliability implications", Microelectronics Reliability, pp.1868~ (2006)
- "ITRS"[URL]
- R. Bhooshan, "Optimum IR Drop Models for Estimation of Metal Resource Requirements for Power Distribution Network", IFIP on VLSI, pp.292~ (2007)
- M. Ketkar, "A microarchitecture based framework for pre- and post-silicon power delivery analysis", Microarchitecture, 42, pp.179~ (2009)
- N. H. Khan, "System level comparison of power delivery design for 2D and 3D ICs 3D System Integration", IEEE 3DIC, pp.1~ (2009)
- B. Amelifard, "Optimal Selection of Voltage Regulator Modules in a Power Delivery Network", IEEE DAC, pp.168~ (2007)
- M. Budnik, "A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies", IEEE Trans. VLSI Systems, 14(12), pp.1336~ (2006)
- C. Wang, "Through co-design to optimize power delivery distribution system using embedded discrete de-coupling capacitor", IEEE CPMT, pp.1~ (2010)
- J. Sun, "3D Power Delivery for Microprocessors and High-Performance ASICs", IEEE APEC (2007)
- G. Schrom, "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90 nm Technology Generation", ISLPED, pp.263~ (2004)
- G. Huang, "Power delivery for 3D chip stacks: Physical modeling and design implication", IEEE EPEP, pp.205~ (2007)
- M. B. Healy, "Distributed TSV Topology for 3-D Power-Supply Networks", IEEE Trans. VLSI systems, pp.1~ (2011)
- S. Kim, "Thick metal layer integrated process flow to improve power delivery and mechanical buffering", ~ (2005)
- A. J. McNamara, "Characterization of nanostructured thermal interface materials", International Journal of Thermal Sciences (2011)
- J. Xu, "Enhancement of thermal interface materials with carbon nanotube arrays", International Journal of Heat and Mass Transfer, 49(9), pp.1658~ (2006)
- A. Hamdan, "Characterization of a liquid-metal microdroplet thermal interface material", Experimental Thermal and Fluid Science, 35(7), pp.1250~ (2011)
- S. N. Paisner, "Nanotechnology and mathematical methods for high-performance thermal interface materials", Global SMT & Packaging, 36 (2008)
- 신형원, "Thermal Via 구조 LED 모듈의 열저항 변화", 마이크로전자 및 패키징학회지, 17(4), pp.95~100 (2010), 한국마이크로전자및패키징학회
- 이우성, "세라믹 패키지 내에서 비아에 따른 열적 거동에 관한 연구", 마이크로전자 및 패키징학회지, 10(1), pp.7~43 (2003), 한국마이크로전자및패키징학회
- J. Darabi, "Development of a chip-integrated micro cooling device", Microelectronics, 34(11), pp.1067~ (2003)
- Y. M. Hung, "Effects of geometric design on thermal performance of star-groove micro-heat pipes", International Journal of Heat and Mass Transfer, 54(5), pp.1198~ (2011)
- J. Vaes, "Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration", Microelectronic Engineering, 88(50), pp.745~ (2011)
- D. Kearney, "A liquid cooling solution for temperature redistribution in 3D IC architectures", Microelectronics (2011)
- F. Schindler-Saefkow, "Thermal Management in a 3D PCB Package with Water Cooling", IEEE ESTC, pp.107~ (2006)
- R. Hon, "Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection", IEEE EPTC, pp.384~ (2005)
- D. Sekar, "A 3D-IC Technology with Integrated Microchannel Cooling", IEEE IITC, pp.13~ (2008)
- C. R. King, Jr., "Electrical and Fluidic C4 Interconnections for Inter-layer Liquid Cooling of 3D ICs", IEEE ECTC, pp.1674~ (2010)
- K. W. Yan, "Double Bump Flip-Chip Assembly", IEEE Trans. EPM, 29(2), pp.119~ (2006)
- M. Topper, "Wafer Level Package using Double Balls", Int. Sym. APM, pp.198~ (2000)
- B. Keser, "Encapsulated double-bump WL-CSP: design and reliability", IEEE ECTC, pp.35~ (2001)
