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A Wide-Range Duty-Independent All-Digital Quadrature-Phase Clock Generator

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초록

A wide-range, input-duty-independent, all-digital qaudrature-phase clock generator is proposed. By using a supply noise filtering block, the power supply noise effect is reduced. Furthermore, because the proposed clock generator consists of all-digital logic gates, it can easily be migrated to a different process within a short time and operate at a low supply voltage. The circuit was fabricated with a 0.18μm 1P4M CMOS technology and operates over the frequency range from 300MHz to 1.5GHz within 5 cycles of the reference clock. Due to its open-loop scheme without jitter accumulation, the increased peak-to-peak jitter from the delay line to the output buffer is only 4.7ps.

Abstract

A wide-range, input-duty-independent, all-digital qaudrature-phase clock generator is proposed. By using a supply noise filtering block, the power supply noise effect is reduced. Furthermore, because the proposed clock generator consists of all-digital logic gates, it can easily be migrated to a different process within a short time and operate at a low supply voltage. The circuit was fabricated with a 0.18μm 1P4M CMOS technology and operates over the frequency range from 300MHz to 1.5GHz within 5 cycles of the reference clock. Due to its open-loop scheme without jitter accumulation, the increased peak-to-peak jitter from the delay line to the output buffer is only 4.7ps.

참고문헌 (17)

  1. D. W. Boerstler, "A low-jitter PLL clock generator for microprocessors with lock range of 340-612MHz", IEEE J. Solid-State Circuits, 34(4), pp.513~519 (1999)
  2. B. Garlepp, "A portable digital DLL for high-speed CMOS interface circuits", IEEE J. Solid-State Circuits, 34(5), pp.632~643 (1999)
  3. A. Alvandpour, "A 3.5GHz 32mw 150nm multiphase clock generator for high-performance microprocessors", ISSCC, Dig. Tech. Papers, pp.112~113 (2003)
  4. C. -C. Chung, "A new DLL-based approach for all-digital multiphase clock generation", IEEE J. Solid-State Circuits, 39(3), pp.469~475 (2004)
  5. H. -H. Chang, "A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop", IEEE J. Solid-State Circuits, 40(3), pp.661~670 (2005)
  6. C. -C. Chung, "An All-Digital Phase-Locked Loop for High-Speed Clock Generation", IEEE J. Solid-State Circuits, 38(2), pp.347~351 (2003)
  7. J. Dunning, "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors", IEEE J. Solid-State Circuits, 30(4), pp.412~422 (1995)
  8. J.-S. Wang, "An Ultra-Low-Power Fast-Lock-in Small-Jitter All-Digital DLL", ISSCC, Dig. Tech. Papers, pp.422~423 (2005)
  9. K. Yamaguchi, "2. 5GHz 4-phase clock generator with scalable and no feedback loop architecture", IEEE J. Solid-State Circuits, 36(11), pp.1666~1672 (2001)
  10. I. Jung, "A 0. 004mm2 portable multiphase clock generator tile for 1. 2GHz RISC microprocessor", IEEE Trans. Circuits Syst. II, Exp. Briefs, 55(2), pp.116~120 (2008)
  11. T. Saeki, "A 1. 3 cycle lock time, non-PLL", DLL jitter suppression clock multiplier based on direct clock cycle interpolation for clock on demand, 2000, pp.35(11), ~
  12. D. Jung, "All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM", IEEE Trans. Circuits Syst. II, Exp. Briefs, 62(11), pp.1023~1027 (2015)
  13. E. Bayram, "1. 5–3. 3 GHz, 0. 0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in 0. 13 μm CMOS", IEEE Trans. Circuits Syst. Ⅰ,, PP(99), pp.1~12 (2017)
  14. Y. Wang, "Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics", IEEE Inter. Symposium on Circuits Syst., pp.1~4 (2016)
  15. H. Chae, "A wide-range duty-independent all-digital multiphase clock generator", Proc. European Solid-State Circuits Conference, pp.186~189 (2007)
  16. R. B. Staszeski, "1. 3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS", IEEE Trans. Circuits Syst. II, Exp. Briefs, 53(3), pp.220~224 (2006)
  17. Y. Lo, "An All-Digital DLL with Dual-Loop Control for Multiphase Clock Generator", Inter. Symposium on Integrated Circuits (2011)

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