A 2.4 GHz Fractional-N Sub-Sampling PLL with a Hybrid Type Phase-Interpolator
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초록
This paper presents a 2.4 GHz sub-sampling fractional-N PLL (SSPLL) with a hybrid type phase-interpolator (HPI). The usage of the HPI alleviates the demanding specification of digi-tal-to-time converter (DTC). The proposed HPI structure is composed of a capacitive and tournament phase-interpolator (PI). This structure generates multi-phases with lower power consumption due to the capacitive PI part which do not con-sume the static power. On the other hand, the capacitive PI is affected by mismatches and parasitic when fine resolution is generated. In order to achieve accuracy with lower power con-sumption, MSB part is divided by capacitive PI and LSB part is divided by the tournament PI. The proposed SSPLL with the HPI is implemented by 65 nm CMOS process. It achieves 162 fs jitter, -247.3 dB figure-of-merit (FoM), and -47 dBc frac-tional spurs with a gain calibration circuit which is based on a least-mean-square (LMS) algorithm.
Abstract
This paper presents a 2.4 GHz sub-sampling fractional-N PLL (SSPLL) with a hybrid type phase-interpolator (HPI). The usage of the HPI alleviates the demanding specification of digi-tal-to-time converter (DTC). The proposed HPI structure is composed of a capacitive and tournament phase-interpolator (PI). This structure generates multi-phases with lower power consumption due to the capacitive PI part which do not con-sume the static power. On the other hand, the capacitive PI is affected by mismatches and parasitic when fine resolution is generated. In order to achieve accuracy with lower power con-sumption, MSB part is divided by capacitive PI and LSB part is divided by the tournament PI. The proposed SSPLL with the HPI is implemented by 65 nm CMOS process. It achieves 162 fs jitter, -247.3 dB figure-of-merit (FoM), and -47 dBc frac-tional spurs with a gain calibration circuit which is based on a least-mean-square (LMS) algorithm.
참고문헌 (7)
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