Two-negative feedback loop PLL with frequency voltage converter loop
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초록
- To reduce the phase noise and jitter of the conventional PLL, the proposed PLL uses frequency voltage converter (FVC). The inner negative feedback loop consisting of a voltage controlled oscillator (VCO) and a frequency voltage converter is nested inside a conventional outer PLL loop. When the output voltage (VCO input voltage) of the loop filter changes, the output voltage of the FVC changes in the opposite direction at a much higher sampling frequency in the negative feedback looped VCO. Thus, whenever the VCO output frequency varies, the FVC works as a compensator and it results in VCO noise reduction. It improves the phase noise characteristic and the stability of PLL. It has been simulated and proved by HSPICE in a CMOS 0.18μm 1.8V process. Measurement result of the two-negative feedback loop PLL fabricated in a one-poly six-metal 0.18μm CMOS process shows approximately 20dB improvement at 1MHz offset from 1GHz carrier frequency.
Abstract
- To reduce the phase noise and jitter of the conventional PLL, the proposed PLL uses frequency voltage converter (FVC). The inner negative feedback loop consisting of a voltage controlled oscillator (VCO) and a frequency voltage converter is nested inside a conventional outer PLL loop. When the output voltage (VCO input voltage) of the loop filter changes, the output voltage of the FVC changes in the opposite direction at a much higher sampling frequency in the negative feedback looped VCO. Thus, whenever the VCO output frequency varies, the FVC works as a compensator and it results in VCO noise reduction. It improves the phase noise characteristic and the stability of PLL. It has been simulated and proved by HSPICE in a CMOS 0.18μm 1.8V process. Measurement result of the two-negative feedback loop PLL fabricated in a one-poly six-metal 0.18μm CMOS process shows approximately 20dB improvement at 1MHz offset from 1GHz carrier frequency.