A 10.3125 Gb/s Deserializer for IEEE 10G-EPON Standard
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The throughput requirement of high-speed interface such as wireline I/O and memory I/O has been increased even if the power budget for the interface circuits has been maintained and decreased. This paper, true single-phase clock logic and half-rate architecture to implement the 16-to-1 10.3125 GB/s deserializer is used to minimize the power consumption with remaining high-speed operation. The design method for essential block such as demultiplexer, clock data recovery circuit, continuous time linear equalizer, decision feedback equalizer and lock detector is also described in paper. The designed deserializer is fabricated through 65nm CMOS process and dissipate about 200mW is satisfied with IEEE standard. The developed deserializer has BER 10-12 with PRBS 2 9 -1.
Abstract
The throughput requirement of high-speed interface such as wireline I/O and memory I/O has been increased even if the power budget for the interface circuits has been maintained and decreased. This paper, true single-phase clock logic and half-rate architecture to implement the 16-to-1 10.3125 GB/s deserializer is used to minimize the power consumption with remaining high-speed operation. The design method for essential block such as demultiplexer, clock data recovery circuit, continuous time linear equalizer, decision feedback equalizer and lock detector is also described in paper. The designed deserializer is fabricated through 65nm CMOS process and dissipate about 200mW is satisfied with IEEE standard. The developed deserializer has BER 10-12 with PRBS 2 9 -1.
참고문헌 (11)
- Akira Tanabe, "0.18-um CMOS 10-Gb", s Multiplexer Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation, 2001, pp.36(6), 988~996
- Jafar Savoj, "A 10-Gb", s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear phase Detector, 2001, pp.36(5), ~
- P. K. Hanumolu, "EQUALIZERS FOR HIGH-SPEED SERIAL LINKS", International Journal of High Speed 44 Electronics and Systems, 15(2) (2005)
- S. Gondi, "Equalization and Clock and Data Recovery Techniques for 10-Gb", s CMOS Serial-Link Receivers, 2007, pp.42(9), ~
- J. S. Choi, "A 0.18-m CMOS 3.5-Gb", s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low Frequency Gain Control Method, 2004, pp.39(3), ~
- S. Kasturia, "Techniques for High-Speed Implementation of Nonlinear Cancellation", IEEE J. On Selected Area in Communications, 9(5) (1991)
- R. S. Kajley, "A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture", IEEE Journal Solid-State Circuit, 32(3) (1997)
- T. Beukema, "A 6.4-Gb", s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization, 2005, pp.40(12), ~
- J. F. Bulzacchelli, "A 10-Gb", s 5-Tap DFE, IEEE Journal Solid-State Circuit, pp.2006, 41(12)[DOI]
- R. S. Kajley, "A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture", IEEE Journal Solid-State Circuit, 32(3) (1997)
- H. wang, "A 21-Gb", s 87-mW Transceiver With FFE, Analog Equalizer in 65-nm CMOS Technology, pp.IEEE Journal Solid-State Circuit, 2010[DOI]