A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in 0.18µm CMOS
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This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18µm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80㎽ at 2.7Gbps rate from a 1.8V supply.
Abstract
This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18µm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80㎽ at 2.7Gbps rate from a 1.8V supply.
참고문헌 (5)
- VESA, "DisplayPort Standard", Version 1, Revision 1a, ~ (2007)
- L. Henrickson, "Low-Power Fully Integrated 10-Gb", s SONET, IEEE Journal of Solid-State Circuits, pp.2003, 38(10)[DOI]
- B.Razavi, "Design of Analog CMOS Integrated Circuits", pp.482~531 (2001), McGraw-Hill
- J. Savoj, "A 10-Gb", s CMOS Clock and Data Recovery Circuit with a half-Rate Binary Phase, IEEE Journal of Solid-State Circuits, pp.2003, 38(1)[DOI]
- Chorng-Sii Hwang, "Dual-Band CDR using a Half-Rate Linear Phase Detector", IEEE International of SOC Conference, pp.51~54 (2009)