A 10 Gbps Optical Receiver Analog Front-End and MZM Driver in 65nm CMOS
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This paper presents a 10 Gbps optical receiver analog front end and a Mach-Zehnder Modulator (MZM) driver in the 65nm technology. The receiver consists of a Shunt Feedback TIA and a Limiting Amplifier with active feedback for bandwidth enhancement. Offset cancellation is also implemented in the feedback path to minimize random and systematic offsets. The modulator driver adopts a dual-stacked buffer topology with dynamic biasing to generate a high voltage swing. The measured trans-impedance gain of the receiver analog front-end is 74.31 dBΩ with a bandwidth of 16.87 GHz. The DC power consumption is 153 mW (including output buffer) with a supply voltage of 1.8 V. The total chip area of the receiver analog front-end is 0.605 mm2. The modulator driver achieves a measured voltage swing of 2.02 Vpp @ 10 Gbps and a simulated average dynamic power of 230 mW @ 10 Gbps with supply voltages of 1.1 and 2.2 V. The total chip area of the modulator driver is 0.434 mm2.
Abstract
This paper presents a 10 Gbps optical receiver analog front end and a Mach-Zehnder Modulator (MZM) driver in the 65nm technology. The receiver consists of a Shunt Feedback TIA and a Limiting Amplifier with active feedback for bandwidth enhancement. Offset cancellation is also implemented in the feedback path to minimize random and systematic offsets. The modulator driver adopts a dual-stacked buffer topology with dynamic biasing to generate a high voltage swing. The measured trans-impedance gain of the receiver analog front-end is 74.31 dBΩ with a bandwidth of 16.87 GHz. The DC power consumption is 153 mW (including output buffer) with a supply voltage of 1.8 V. The total chip area of the receiver analog front-end is 0.605 mm2. The modulator driver achieves a measured voltage swing of 2.02 Vpp @ 10 Gbps and a simulated average dynamic power of 230 mW @ 10 Gbps with supply voltages of 1.1 and 2.2 V. The total chip area of the modulator driver is 0.434 mm2.
참고문헌 (9)
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