A 1Gbps reference-less clock and data recovery using injection phase locked loop
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Injection Locking Phase-Locked Loop (IL-PLL) technique applied to 0.7 ~ 1.3Gb/s Clock and Data Recovery (CDR) is presented in this paper. Conventional CDR implemented by adding a Frequency Locked Loop (FLL) in a PLL in order to achieve a sufficiently large dynamic range. The proposed structure achieves wide input data rate range and low power consumption by implementing a FLL with digital circuits. A PLL to recover the clock and data was implemented digitally. The advantage of digital circuit design is a small area, low power and the ease of re-design. The proposed reference-less CDR is implemented in Magna Foundry 0.18um CMOS process. The measurement result is that the phase noise is about -108.57dBc/Hz at 1Mhz offset. The area of chip is a 0.55〖mm〗^2 and the power consumption with 1.8V supply voltage is 17.5mW when CDR operate at 1Gb/s of input data stream.
Abstract
Injection Locking Phase-Locked Loop (IL-PLL) technique applied to 0.7 ~ 1.3Gb/s Clock and Data Recovery (CDR) is presented in this paper. Conventional CDR implemented by adding a Frequency Locked Loop (FLL) in a PLL in order to achieve a sufficiently large dynamic range. The proposed structure achieves wide input data rate range and low power consumption by implementing a FLL with digital circuits. A PLL to recover the clock and data was implemented digitally. The advantage of digital circuit design is a small area, low power and the ease of re-design. The proposed reference-less CDR is implemented in Magna Foundry 0.18um CMOS process. The measurement result is that the phase noise is about -108.57dBc/Hz at 1Mhz offset. The area of chip is a 0.55〖mm〗^2 and the power consumption with 1.8V supply voltage is 17.5mW when CDR operate at 1Gb/s of input data stream.
참고문헌 (20)
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