광통신용 10Gbps CMOS 수신기 회로 설계
Design of 10Gbps CMOS Receiver Circuits for Fiber-Optic Communication
1
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.
Abstract
This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.
참고문헌 (5)
- Sung Min Park, "1.25Gb", s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications, 2004, pp.39, 112~121
- Sherif Galal, "10Gb", s Limiting Amplifier and Laser, IEEE JSSC, pp.2003, 38[DOI]
- K.Azadet, "Equalization and FEC Techniques for Optical Transceivers", IEEE JSSC, 37, pp.317~327 (2002)
- J.Cao, "OC-192 Transmitter and Receiver in Standard 0.18um CMOS", IEEE JSSC, 37, pp.1768~1780 (2002)
- S.Byun, "A 10-Gb", s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector, 2006, pp.41, 2566~2576