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A 7–8.5 GHz LC Voltage-Controlled Oscillator with –111.7 dBc/Hz Phase Noise at 1-MHz offset for Ultra-Low-Jitter Phase-Locked Loop

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초록

This work presents an area efficiency LC voltage-controlled oscillator for an ultra-low-jitter phase-locked loop. Using a 3-turn area-compact spiral, the VCO achieve area-efficient without degrading LC-tank quality factor. The negative transconductance cell was NMOS type so that the start-up was done in 3ns. This work also includes a tail inductor for the noise filtering. As a result, the measured phase noise at 8 GHz was -111.7 dBc/Hz with 1 MHz offset and -134.9 dBc/Hz with 10 MHz offset. The power consumption was only 2.7 mW at 8 GHz. Also, the die area was less than 0.03 mm2.

Abstract

This work presents an area efficiency LC voltage-controlled oscillator for an ultra-low-jitter phase-locked loop. Using a 3-turn area-compact spiral, the VCO achieve area-efficient without degrading LC-tank quality factor. The negative transconductance cell was NMOS type so that the start-up was done in 3ns. This work also includes a tail inductor for the noise filtering. As a result, the measured phase noise at 8 GHz was -111.7 dBc/Hz with 1 MHz offset and -134.9 dBc/Hz with 10 MHz offset. The power consumption was only 2.7 mW at 8 GHz. Also, the die area was less than 0.03 mm2.

참고문헌 (6)

  1. X. Gao, "A 2.2 GHz sub-sampling PLL with 0.16 psrms jitter and −125 dBc", Hz in-band phase noise at 700μW loop-components power, 2010, 139~140
  2. T. Seong, "A −242 dB FOM and −75 dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC", IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.396~398 (2018)
  3. Y. Lee, "A −240dB-FoM jitter and −115 dBc", Hz PN @ 100kHz, 7.7 GHz Ring-DCO-Based Digital PLL Using P, IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.2020[DOI]
  4. F. Gardner, "Charge-pump phase-lock loops", IEEE Trans. Commun, 28(11), pp.1849~1858 (1980)
  5. J. Kim, "A 76 fsrms jitter and −40 dBc integrated-phase-noise 28-to31 GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization", IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.258~260 (2019)
  6. E. Hegazi, "A filtering technique to lower LC oscillator phase noise", IEEE Journal of Solid-State Circuits, 36(12), pp.1921~1930 (2001)

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