Design of FET structure for high frequency in 65nm CMOS process
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New designs of FET are proposed with built-in based and all revised transistor for lower resistance of gate and lower capacitances of Cgd to design Millimeter-wave Power Amplifier (PA) for high consistency with simulation. Measured maximum available gain is 9.41dB at 2m x24 all revised type transistor. The driving voltage of FET is 1.2V and gate voltage is 1V in 65nm normal CMOS process.
Abstract
New designs of FET are proposed with built-in based and all revised transistor for lower resistance of gate and lower capacitances of Cgd to design Millimeter-wave Power Amplifier (PA) for high consistency with simulation. Measured maximum available gain is 9.41dB at 2m x24 all revised type transistor. The driving voltage of FET is 1.2V and gate voltage is 1V in 65nm normal CMOS process.
참고문헌 (6)
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