Design of a High-Hole-Mobility Ge Transistor for Si-Driven Heterogeneous Integrated Circuits
0
조회
0
다운로드
0
인용
0
참고문헌
초록
A high-hole-mobility transistor (HHMT) with an intrinsic Ge channel is optimally designed and its DC and high-frequency performances are investigated by technology computer-aided design (TCAD) simulation. An HHMT with a Ge channel and AlGaAs barrier on the Si substrate is characterized with a particular interest in the barrier design. More specifically, barrier doping concentration, total barrier thickness, and high-doped barrier thickness are considered as the critical design variables. A permissibly optimized device demonstrates cut-off frequency (fT) of 20 GHz and maximum oscillation frequency (fmax) of 80 GHz at a channel length of 90 nm. The Ge HHMT with an AlGaAs barrier has the potential to be a component in the heterogeneously integrated monolithic circuits made of Si, group-IV alloys, and III-V compound semiconductors where electronic and optical devices can be simultaneously integrated with enhanced device performances.
Abstract
A high-hole-mobility transistor (HHMT) with an intrinsic Ge channel is optimally designed and its DC and high-frequency performances are investigated by technology computer-aided design (TCAD) simulation. An HHMT with a Ge channel and AlGaAs barrier on the Si substrate is characterized with a particular interest in the barrier design. More specifically, barrier doping concentration, total barrier thickness, and high-doped barrier thickness are considered as the critical design variables. A permissibly optimized device demonstrates cut-off frequency (fT) of 20 GHz and maximum oscillation frequency (fmax) of 80 GHz at a channel length of 90 nm. The Ge HHMT with an AlGaAs barrier has the potential to be a component in the heterogeneously integrated monolithic circuits made of Si, group-IV alloys, and III-V compound semiconductors where electronic and optical devices can be simultaneously integrated with enhanced device performances.
참고문헌 (21)
- C. Claeys, "Germanium-Based Technologies: From Materials to Devices", pp.309~ (2007), Elsevier
- "Process Integration, Devices, and Structures (PIDS) Chapter, International Technology Roadmap for Semiconductors (ITRS)" (2013)[URL]
- P. Zimmerman, "High performance Ge pMOS devices using a Si-compatible process flow", IEDM Tech. Dig., pp.1~4 (2006)
- S. Takagi, "High Mobility CMOS Technologies using III-V", Ge Channels, 2013, ~
- R. Zhang, "High-Mobility Ge PMOSFET With 1-nm EOT Al2O3", GeOx, IEEE Transactions on Electron Devices, pp.2012, 59(12)[DOI]
- S. Cho, "Silicon-compatible high-hole-mobility transistor with an undoped germanium channel for low-power application", Applied Physics Letters, 103(22) (2013)
- S. Cho, "Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation", Applied Physics Letters, 99(24) (2011)
- J. W. Goodman, "Optical Interconnections for VLSI Systems", Proceeding of the IEEE, 72(7), pp.850~866 (1984)
- D. A. B. Miller, "Optics for low-energy communication inside digital processors : quantum detectors, sources, and modulators as efficient impedance converters", Optics Letters, 14(2), pp.146~148 (1989)
- D. A. B. Miller, "Rationale and Challenges for Optical Interconnects to Electronic Chips", Proc. IEEE, 88(6), pp.728~749 (2000)
- D. A. B. Miller, "Device Requirements for Optical Interconnects to Silicon Chips", Proceeding of the IEEE, 97(7), pp.1166~1185 (2009)
- S. Cho, "Process Considerations for 80-GHz High-Performance p-i-n Silicon Photodetector for Optical Interconnect", Journal of Semiconductor Technology and Science, 12(3), pp.370~376 (2012)
- V. A. Shah, "High quality relaxed Ge layers grown directly on Si(001)substrate", Solid-State Electronics, 62(1), pp.189~194 (2011)
- K. W. Ng, "Unconventional Growth Mechanism for Monolithic Integration of III-V on Silicon", ACS Nano, 7(1), pp.100~107 (2012)
- J. Xie, "Synthesis, Stability Range, and Fundamental Properties of Si-Ge-Sn Semiconductors Grown Directly on Si(100)and Ge(100)Platforms", Chemistry of Materials, 22(12), pp.3779~3789 (2010)
- K. Majumdar, "Mapping Defect Density in MBE Grown In0. 53Ga0. 47As Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics", IEEE Transactions on Electron Devices, 61(6) (2014)
- 금동민, "Temperature-Dependent Instabilities of DC characteristics in AlGaN", GaN-on-Si Heterojunction Field Effect Transistors, 2014, pp.14(5), 682~687[DOI]
- S. Cho, "Silicon-Compatible Bulk-Type Compound Junctionless Field-Effect Transistor", IEEE International Semiconductor Device Research Symposium(ISDRS), pp.1~2 (2011)
- S. Cho, "Room-temperature electroluminescence from germanium in an Al0. 3Ga0. 7As", Ge heterojunction light-emitting diode by Γ-valley transport, 2012, pp.20(14), 14921~14927
- HEMTs, "Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs", pp.1999, W. Lin
- J. S. Harris Jr., "Class Notes from EE327 Properties of Semiconductor Materials", pp.2013