A 33.3% Power Efficiency RF Energy Harvester with -25dBm Sensitivity using Threshold Compensation Scheme
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This paper presents an ultra-low power RF-DC voltage multiplier using auxiliary transistors block to dynamically control the threshold voltage of the main chain transistors. The proposed scheme enhances the forward conduction current and reduces the reverse current by controlling the gate to source voltage of the main chain transistors. The proposed 5-stage scheme attains maximum post-layout simulated power conversion efficiency (PCE) of 33.3% at -16dBm input level and delivers 2.63 V output DC voltage to 1MΩ load. The proposed RF-DC voltage multiplier has been designed in a standard 180 nm CMOS technology.
Abstract
This paper presents an ultra-low power RF-DC voltage multiplier using auxiliary transistors block to dynamically control the threshold voltage of the main chain transistors. The proposed scheme enhances the forward conduction current and reduces the reverse current by controlling the gate to source voltage of the main chain transistors. The proposed 5-stage scheme attains maximum post-layout simulated power conversion efficiency (PCE) of 33.3% at -16dBm input level and delivers 2.63 V output DC voltage to 1MΩ load. The proposed RF-DC voltage multiplier has been designed in a standard 180 nm CMOS technology.
참고문헌 (13)
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