Design of a Continuous-Time Delta-Sigma Modulator for Bio-signal Acquisition
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초록
This work presents a design methodology of a low-noise and low-power continuous-time delta-sigma modulator (CT DSM) architecture for bio-signal acquisition. Along with the 2nd-order CT loop filter architecture, a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is used as a quantizer to achieve power efficiency. The incremental operation is added to enable multi-channel processing. Designed and fabricated in a 180nm CMOS process, the proposed architecture achieves 80.1dB SNDR in a 250kHz bandwidth (BW) under a 1.8V supply. With a power consumption of 2mW, the proposed architecture has a Schreier Figure of Merit (FoMS) of 161dB.
Abstract
This work presents a design methodology of a low-noise and low-power continuous-time delta-sigma modulator (CT DSM) architecture for bio-signal acquisition. Along with the 2nd-order CT loop filter architecture, a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is used as a quantizer to achieve power efficiency. The incremental operation is added to enable multi-channel processing. Designed and fabricated in a 180nm CMOS process, the proposed architecture achieves 80.1dB SNDR in a 250kHz bandwidth (BW) under a 1.8V supply. With a power consumption of 2mW, the proposed architecture has a Schreier Figure of Merit (FoMS) of 161dB.
참고문헌 (7)
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- M. A. Mokhtar, "A 94. 3-dB SFDR, 91. 5-dB DR, and 200-kS", s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback, 2019, pp.2(9), 87~90
- P. Vogelmann, "A dynamic power reduction technique for incremental ΔΣ modulators", IEEE J. Solid-State Circuits, 54(5), pp.1455~1467 (2019)
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- J. Wagner, "An Automated Design Environment for CT Incremental Sigma-Delta ADCs", 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.1~4 (2020)
- S. Pavan, "Understanding Delta-Sigma Data Converters" (2017), IEEE Press
- B. P. Ginsburg, "An energy-efficient charge recycling approach for a SAR converter with capacitive DAC", 2005 IEEE International Symposium on Circuits and Systems, 1, pp.184~187 (2005)