Continuous-time delta-sigma modulator using asynchronous SAR quantizer and digital ΔΣ Truncator
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
As the demand for IoT related devices has increased recently, the demand for voice sensors used in these devices is increasing. Low power is a key factor because these devices have to run on batteries for long periods of time. A delta-sigma modulator is best suited for analog-to-digital converters used in the voice signal band because resolution is more important than speed. This delta sigma modulator requires a high SQNR in order to obtain high resolution, indicating that a high bit number quantizer is required. However, a high bit number quantizer requires a large number of comparators and DACs, which increases power consumption and takes up a large area. In this paper, to achieve low noise and low power dissipation, 3rd order continuous time delta-sigma (DS) ADC with a 6-bit asynchronous successive approximation register (ASAR) quantizer and a digital delta-sigma truncator which reduce a number of DACs is presented. The designed ADC front-end has been implemented through a 180 nm CMOS process and achieved 86 dB SNR and 76 dB SNDR over a 20 kHz signal band. The total chip dissipates a power of 170μW from a 1.5 V supply.
Abstract
As the demand for IoT related devices has increased recently, the demand for voice sensors used in these devices is increasing. Low power is a key factor because these devices have to run on batteries for long periods of time. A delta-sigma modulator is best suited for analog-to-digital converters used in the voice signal band because resolution is more important than speed. This delta sigma modulator requires a high SQNR in order to obtain high resolution, indicating that a high bit number quantizer is required. However, a high bit number quantizer requires a large number of comparators and DACs, which increases power consumption and takes up a large area. In this paper, to achieve low noise and low power dissipation, 3rd order continuous time delta-sigma (DS) ADC with a 6-bit asynchronous successive approximation register (ASAR) quantizer and a digital delta-sigma truncator which reduce a number of DACs is presented. The designed ADC front-end has been implemented through a 180 nm CMOS process and achieved 86 dB SNR and 76 dB SNDR over a 20 kHz signal band. The total chip dissipates a power of 170μW from a 1.5 V supply.
참고문헌 (5)
- Schreier, R., "Understanding delta-sigma data converters" (2005), IEEE Press
- D conversion, "Continious-time sigma-delta A", pp.2006, Ortmanns, M.
- Yafei Ye, "A 120dB SNDR Audio Sigma-Delta Modulator with an Asynchronous SAR Quantizer", Circuits and Systems (ISCAS), 2012 IEEE International Symposium on Circuits and Systems (ISCAS)
- C-C Liu, "A 10-bit 50-MS", s SAR ADC with a monotonic capacitor switching procedure, 2010, pp.45, 731~740
- Hung-Chieh Tsai, "A 64-fJ", Conv.-Step Continuous-Time ΣΔ Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital ΔΣ Truncator, 2013, pp.48(11), 2637~2648