Two-Stage Distributed Amplifier and Cascaded Single-Stage Distributed Amplifier in 65 nm CMOS Process
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This work presents a 2-stage distributed amplifier (DA) and a 2-stage cascaded single-stage distributed amplifier (CSSDA) in Samsung 65 nm CMOS technology. They are designed in cascode configuration to obtain broad bandwidth and high gain, and m-derived filter configuration is used for compact layout. The measurement results show a peak gain of 10 dB of 2-stage DA and 13 dB of 2-satge CSSDA with the 3-dB bandwidth from 5 GHz to 20 GHz. S11 and S22 are better than -10 dB over the entire bandwidth. The chip sizes are 720 × 540 μm2 and 580 × 450 μm2 for the 2-stage DA and the 2-stage CSSDA, respectively.
Abstract
This work presents a 2-stage distributed amplifier (DA) and a 2-stage cascaded single-stage distributed amplifier (CSSDA) in Samsung 65 nm CMOS technology. They are designed in cascode configuration to obtain broad bandwidth and high gain, and m-derived filter configuration is used for compact layout. The measurement results show a peak gain of 10 dB of 2-stage DA and 13 dB of 2-satge CSSDA with the 3-dB bandwidth from 5 GHz to 20 GHz. S11 and S22 are better than -10 dB over the entire bandwidth. The chip sizes are 720 × 540 μm2 and 580 × 450 μm2 for the 2-stage DA and the 2-stage CSSDA, respectively.
참고문헌 (12)
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