단일 에지 이진위상검출기를 사용한저 지터 클록 데이터 복원 회로 설계
Design of low jitter CDR using a single edge binary phase detector
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초록
본 논문은 CDR회로의 지터 감소를 위해 변형된 이진 위상검출기(뱅뱅위상 검출기- BBPD) 회로를 제안하였다. 제안된 PD는 하나의 에지를 사용함으로써 전압리플을 줄여, 제안한 PD를 적용하여 설계한 CDR회로는 감소된 지터 특성을 보였다. CMOS 0.13um 공정을 사용하여 설계하였고 제안한 위상검출기를 포함하는 클럭데이터 복원회로는 모의실험결과 16.9mW 전력소비에 peak-peak 지터는 10.96ps, rms 지터는 0.89ps을 보였다.
Abstract
This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu 0.13μm CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.
참고문헌 (6)
- J. Lee, "Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits", IEEE Journal of Solid State Circuits, 39(9), pp.1571~1580 (2004)
- Rennie David, "Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits", International Symposium on Quality Electronic Design, pp.305~310 (2007)
- David Rennie, "A Novel Tri-State Binary Phase Detector", IEEE International Symposium on Circuits and Systems, pp.185~188 (2007)
- Jae-Wook Yoo, "A CMOS 5.4", 3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector, 2011, pp.33(5), 752~758[DOI]
- Adrian Maxim, "Low-Voltage CMOS Charge-Pump PLL Architecture for Low Jitter Operation", ESSCIRC, pp.423~426 (2002)
- Hwang-Cherng Chow, "A high performance peak detector sample and hold circuit for detecting power supply noise", IEEE Asia Pacific Conference, pp.672~675 (2008)