Atmospheric neutron inducing single event effects on AI chips manufacturing with 8 nm FinFET

Abstract

With the rapid advancement of artificial intelligence (AI) chips in diverse applications, single event effects (SEE) caused by high energy particles in ambient environment have emerged as a critical concern. Among these, static random access memory (SRAM) cells integrated into AI chips exhibit heightened sensitivity to SEEs due to their high density bit cell architectures. This study investigates the SEE susceptibility of SRAM cells fabricated using an 8 nm FinFET technology integrated into the AI chip, leveraging the atmospheric neutron irradiation spectrometer (ANIS) at the China spallation neutron source (CSNS) as the irradiation platform. During the irradiation, comprehensive SEE tests were conducted under varying operational conditions, with results systematically compared to those from 14 nm to 28 nm process nodes. The findings reveal that as semiconductor technology scales from 14 nm to 8 nm, the single event upset (SEU) cross section per bit decreases while the nonsingle bit upset proportion goes up. During the experiments, multiple cell upsets (MCUs) were detected with a maximum cluster size of seven. While the 8 nm FinFET architecture enhances intrinsic resistance to SEUs by narrowing the charge collection region, the reduced technology node may paradoxically exacerbate MCU susceptibility, leading to a higher effective MCU ratio. Consequently, the SEE exhibits a non-monotonic relationship with process scaling, highlighting the need for advanced error mitigation strategies in advanced AI chips.