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System-on-Chip Single Event Effect hardening design and validation using proton irradiation

Li Yang|Guo Gang|He Chaohui|Yang Weitao|Wu Longsheng
한국원자력학회 (Korean Nuclear Society)|2023.03|Nuclear Engineering and Technology|제55권 제3호|pp. 1015-1020|DOI 10.1016/j.net.2022.10.034

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키워드

System-on-ChipProton irradiationAsymmetric multi-processingSingle event effect
주제분류원자력공학

초록

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

Abstract

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

참고문헌 (31)

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