Radiation tolerant capacitor-SRAM without area overhead
2
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process
Abstract
In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process
참고문헌 (34)
- S. Pal, "Highly stable low power radiation hardened memory-by-design SRAM for space applications", IEEE Transactions on Circuits and Systems II: Express Briefs, 68(6), pp.2147~2151 (2021)[DOI]
- L.D. Trang Dang, "Studying the variation effects of radiation hardened Quatro SRAM bit-cell", IEEE Trans. Nucl. Sci, 63(4), pp.2399~2401 (2016)[DOI]
- J. Wang, "Study of SEU sensitivity of SRAM-based radiation monitors in 65-nm CMOS", IEEE Trans. Nucl. Sci, 68(5), pp.913~920 (2021)[DOI]
- S.M. Jahinuzzaman, "A soft error tolerant 10T SRAM bitcell with differential read capability", IEEE Trans. Nucl. Sci, 56(6), pp.3768~3773 (2009)[DOI]
- M.S.M. Siddiqui, "SRAM radiation hardening through self-refresh operation and error correction", IEEE Trans. Device Mater. Reliab, 20(2), pp.468~474 (2020)[DOI]
- P.E. Dodd, "Basic mechanisms and modeling of single-event upset in digital microelectronics", IEEE Trans. Nucl. Sci, 50(3), pp.583~602 (2003)[DOI]
- J.R. Schwank, "Radiation effects in SOI technologies", IEEE Trans. Nucl. Sci, 50(3), pp.522~538 (2003)[DOI]
- P.E. Dodd, "Current and future challenges in radiation effects on CMOS electronics", IEEE Trans. Nucl. Sci, 57(4), pp.1747~1763 (2010)[DOI]
- L.D. Trang Dang, "We-quatro: radiation-hardened SRAM cell with parametric process variation tolerance", IEEE Trans. Nucl. Sci, 64(9), pp.2489~2496 (2017)[DOI]
- T. Calin, "Upset hardened memory design for submicron CMOS technology", IEEE Trans. Nucl. Sci, 43(6), pp.2874~2878 (1996)[DOI]
- Q. Wu, "Supply voltage dependence of heavy ion induced SEEs on 65 nm CMOS bulk SRAMs", IEEE Trans. Nucl. Sci, 62(4), pp.898~1904 (2015)[DOI]
- S. S. Dohar, "A 1.2 V, highly reliable RHBD 10T SRAM cell for aerospace application", IEEE Trans. Electron. Dev, 68(5), pp.2265~2270 (2021)[DOI]
- E. Seevinck, "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid State Circ, 22(5), pp.748~754 (1987)[DOI]
- B.H. Calhoun, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation", IEEE J. Solid State Circ, 42(3), pp.680~688 (2007)[DOI]
- C.B. Kushwah, "A single-ended with dynamic feedback control 8T subthreshold SRAM cell", IEEE Trans. Very Large Scale Integr. Syst, 24(1), pp.373~377 (2016)[DOI]
- D. Khalil, "Accurate estimation of SRAM dynamic stability", IEEE Trans. Very Large Scale Integr. Syst, 16(12), pp.1639~1647 (2008)[DOI]
- S.O. Toh, "Characterization of dynamic SRAM stability in 45 nm CMOS", IEEE J. Solid State Circ, 46(11), pp.2702~2712 (2011)[DOI]
- J. Guo, "Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology", IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), pp.1994~2001 (2014)[DOI]
- S. Pal, "Soft-error-immune read-stability-improved SRAM for multi-node upset tolerance in space applications", IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), pp.3317~3327 (2021)[DOI]
- J. Jiang, "Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications", IEEE Transactions on Circuits and Systems I: Regular Papers, 66(3), pp.967~977 (2019)[DOI]
- C. Qi, "A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets", IEEE Trans. Device Mater. Reliab, 16(3), pp.388~395 (2016)[DOI]
- "Critical Charge and Threshold LET"[URL]
- B. Ciftcioglu, "Integrated silicon PIN photodiodes using deep N-well in a standard 0.18-μ m CMOS technology", J. Lightwave Technol, 27(15), pp.3303~3313 (2009)[DOI]
- "Single Event Upset Test Facility"[URL]
- S.-B. Kim, "Stability analysis of 6T SRAM at deep cryogenic temperature for quantum computing applications", IEEE International Symposium on Circuits and Systems, pp.1~5 (2023)
- Gandha Satria Adi, "Simulation-based analysis of total ionizing dose effects on low noise amplifier for wireless communications", Nucl. Eng. Technol (2023)[DOI]
- Minuk Seung, "Radiationhardened-by-design preamplifier with binary weighted current source for radiation detector", Nucl. Eng. Technol (2023)[DOI]
- Minuk Seung, "in-core neutron detection system using a dualmode self-reset preamplifier with the micro-pocket fission detector", IEEE Trans. Instrum. Meas, 72, pp.1~10 (2023)
- Minuk Seung, "Cold junction compensation technique of thermocouple thermometer using radiation-hardenedby-design voltage reference for harsh radiation environment", IEEE Trans. Instrum. Meas, 71, pp.1~7 (2022)
- Hyuntak Jeon, "Radiation-hardened sensor interface circuit for monitoring severe accidents in nuclear power plants", IEEE Trans. Nucl. Sci, 67(7), pp.1738~1745 (2020)
- Changyeop Lee, "Integrated circuit design for radiation-hardened charge-sensitive amplifier survived up to 2mrad", MDPI Sensors, 20(10), pp.2765~ (2020)
- Sunghoon Kim, "TID-tolerant inverter designs for radiation-hardened digital systems", Nucl. Instrum. Methods Phys. Res, 954, pp.161473~ (2020)
- A. Javanainen, "Linear energy transfer of heavy ions in silicon", IEEE Trans. Nucl. Sci, 54(4), pp.1158~1162 (2007)[DOI]
- Y. Chiang, "Lineal energy of proton in silicon by a microdosimetry simulation", Appl. Sci, 11, pp.1113~ (2021)[DOI]