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Radiation effects on multi-channel Forksheet-FET and Nanosheet-FET considering the bottom dielectric isolation scheme

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초록

This study analyzes the single-event transient (SET) characteristics of alpha particles on multi-channel Forksheet- FET and Nanosheet-FET at the device and circuit levels through 3D TCAD simulations. The study investigates the differences in SET responses based on the energy and incident position of incoming alpha particles, considering the structural variances between Forksheet-FET and Nanosheet-FET, as well as the presence or absence of bottom dielectric isolation (BDI) in the fabrication process. Specifically, the introduction of BDI is observed to significantly suppress the voltage drop caused by ‘unintended’ current, as it can block the substantial electron-hole pairs (EHP) generated by injected alpha particles in the bulk substrate from reaching the FET terminals. Furthermore, it was confirmed that the size of abnormal current decreases as the energy of the injected alpha particle increases. Additionally, evaluating the response to SET based on the fundamental logic circuit, the CMOS inverter, revealed relatively small abnormal voltage drops for both Forksheet and Nanosheet when BDI was applied, confirming high immunity to radiation effects. Moreover, it can be observed that the application of BDI enhances reliability from a memory perspective by effectively suppressing voltage flips in the SRAM’s crosscoupled latch circuit.

Abstract

This study analyzes the single-event transient (SET) characteristics of alpha particles on multi-channel Forksheet- FET and Nanosheet-FET at the device and circuit levels through 3D TCAD simulations. The study investigates the differences in SET responses based on the energy and incident position of incoming alpha particles, considering the structural variances between Forksheet-FET and Nanosheet-FET, as well as the presence or absence of bottom dielectric isolation (BDI) in the fabrication process. Specifically, the introduction of BDI is observed to significantly suppress the voltage drop caused by ‘unintended’ current, as it can block the substantial electron-hole pairs (EHP) generated by injected alpha particles in the bulk substrate from reaching the FET terminals. Furthermore, it was confirmed that the size of abnormal current decreases as the energy of the injected alpha particle increases. Additionally, evaluating the response to SET based on the fundamental logic circuit, the CMOS inverter, revealed relatively small abnormal voltage drops for both Forksheet and Nanosheet when BDI was applied, confirming high immunity to radiation effects. Moreover, it can be observed that the application of BDI enhances reliability from a memory perspective by effectively suppressing voltage flips in the SRAM’s crosscoupled latch circuit.

참고문헌 (24)

  1. G. E. Moore, "Cramming more components onto integrated circuits", Proc. IEEE, 86(1), pp.82~85 (1998)
  2. R.H. Dennard, "Design of ion-implanted MOSFET’s with very small physical dimensions", IEEE J. Solid State Circ, 9(5), pp.256~268 (1974)[DOI]
  3. N. Loubet, "Stacked Nanosheet gate-all-around transistor to enable scaling beyond FinFET", 2017 Symposium on VLSI Technology (2017), IEEE
  4. Daniel Nagy, "Benchmarking of FinFET, Nanosheet, and nanowire FET architectures for future technology nodes", IEEE Access, 8, pp.53196~53202 (2020)
  5. Lei Cao, "Bottom dielectric isolation to suppress sub-fin parasitic channel of vertically-stacked horizontal gate-all-around Si nanosheets devices", 2022 China Semiconductor Technology International Conference (CSTIC) (2022), IEEE
  6. J. Zhang, "Full bottom dielectric isolation to enable stacked Nanosheet transistor for low power and high performance applications", 2019 IEEE International Electron Devices Meeting (IEDM) (2019), IEEE
  7. Pieter Weckx, "Novel Forksheet device architecture as ultimate logic scaling device towards 2nm", 2019 IEEE International Electron Devices Meeting (IEDM) (2019), IEEE
  8. H. Mertens, "Forksheet FETs with bottom dielectric isolation, self-aligned gate cut, and isolation between adjacent source-drain structures", 2022 International Electron Devices Meeting (IEDM) (2022), IEEE
  9. Robert C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies", IEEE Trans. Device Mater. Reliab, 5(3), pp.305~316 (2005)
  10. Jianjun Chen, "Novel layout technique for N-hit single-event transient mitigation via source-extension", IEEE Trans. Nucl. Sci, 59(6), pp.2859~2866 (2012)
  11. Kodai Yamada, "Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process", 2018IEEE International Reliability Physics Symposium (IRPS) (2018), IEEE
  12. Gaurav Kaushal, "Radiation effects in Si-NW GAA FET and CMOS inverter : a TCAD simulation study", IEEE Trans. Electron. Dev, 59(5), pp.1563~1566 (2012)
  13. Jungsik Kim, "Single-event transient in FinFETs and nanosheet FETs", IEEE Electron. Device Lett, 39(12), pp.1840~1843 (2018)
  14. Nischal Anand, "TCAD-based analysis of nanosheet and forksheet FET electrical characteristics in the presence of gamma and heavy ion radiation", 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC) (2023), IEEE
  15. Xun-Ting Zheng, "Improved radiation hardness for nanosheet FETs with partial bottom dielectric isolation", 2023 Silicon Nanoelectronics Workshop (SNW) (2023), IEEE
  16. Patrick Nsengiyumva, "Analysis of bulk FinFET structural effects on singleevent cross sections", IEEE Trans. Nucl. Sci, 64(1), pp.441~448 (2016)
  17. Patrick Nsengiyumva, "A comparison of the SEU response of planar and FinFET D flip-flops at advanced technology nodes", IEEE Trans. Nucl. Sci, 63(1), pp.266~272 (2016)
  18. Yung-Chun Wu, "3D TCAD Simulation for CMOS Nanoeletronic Devices", pp.1~17 (2018)
  19. Michiel Vandemaele, "Simulation comparison of hot-carrier degradation in nanowire, Nanosheet and Forksheet FETs", 2022 IEEE International Reliability Physics Symposium (IRPS) (2022), IEEE
  20. Changhyun Yoo, "Analysis of self-heating effects in multi-Nanosheet FET considering bottom isolation and package options", IEEE Trans. Electron. Dev, 69(3), pp.1524~1531 (2022)
  21. Daisuke Kobayashi, "Scaling trends of digital single-event effects : a survey of SEU and SET parameters and comparison with transistor performance", IEEE Trans. Nucl. Sci, 68(2), pp.124~148 (2020)
  22. Youngsoo Seo, "Prediction of alpha particle effect on 5-nm vertical field-effect transistors", IEEE Trans. Electron. Dev, 66(1), pp.806~809 (2018)
  23. Jungmin Hong, "Alpha particle effect on multi-nanosheet tunneling fieldeffect transistor at 3-nm technology node", Micromachines, 10(12), pp.847~ (2019)
  24. M. Pocaterra, "A unified model for TCAD simulation of the charge generated in semiconductors by low-energy alpha particles and protons", Microelectron. Reliab, 138, pp.114725~ (2022)

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