Novel Design of 8T Ternary SRAM for Low Power Sensor System
0
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTIand NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic ‘0’ or ‘2,’the proposed SRAM cell operates the same way as conventional binary SRAM. For logic ‘1,’ it works differently as storage nodes oneach side retain voltages of VDD/2 and VDD, respectively, using the subthreshold current of two additional transistors. By applying theternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and theproposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in staticpower consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of thecell operation when VDD is set to 0.9 V
Abstract
In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTIand NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic ‘0’ or ‘2,’the proposed SRAM cell operates the same way as conventional binary SRAM. For logic ‘1,’ it works differently as storage nodes oneach side retain voltages of VDD/2 and VDD, respectively, using the subthreshold current of two additional transistors. By applying theternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and theproposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in staticpower consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of thecell operation when VDD is set to 0.9 V
참고문헌 (16)
- C. J. Jhang, "Challenges and trends of SRAM-based computing-in-memory for AI edge devices", IEEE Trans. Circuits Syst. I Regul. Pap., 68(5), pp.1773~1786 (2021)
- J. Y. Kim, "Processing-in-Memory for AI", pp.1~165 (2022), Springer
- H. N. Patel, "Optimizing SRAM bitcell reliability and energy for IoT applications", Proc. of the 17th Int. Symp. Qual. Electron. Design, pp.12~17 (2016)
- J. R. Dinesh Kumar, "Performance investigation of various SRAM cells for IoT based wearable biomedical devices", Proc. of 5th International Conference Information, Communication & Computing Technology(ICICCT-2020), pp.573~588 (2021)
- V. Sharma, "A write?improved low?power 12T SRAM cell for wearable wireless sensor nodes", Int. J. Circuit Theory Appl., 46(12), pp.2314~2333 (2018)
- H. Lam, "Pseudo multi-port SRAM circuit for image processing in display drivers", IEEE Trans. Circuits Syst. Video Technol., 31(5), pp.2056~2062 (2020)
- Y. Taur, "CMOS design near the limit of scaling", IBM J. Res. Develop., 46(2.3), pp.213~222 (2002)
- S. Kim, "A logic synthesis methodology for low-power ternary logic circuits", IEEE Trans. Circuits Syst. I Regul. Pap., 67(9), pp.3138~3151 (2020)
- J. Yoon, "Optimizing ternary multiplier design with fast ternary adder", IEEE Trans. Circuits Syst. II Express Briefs, 70(2), pp.766~770 (2022)
- V. A. Bespalov, "Possibilities and limitations of CMOS Technology for the production of various Microelectronic systems and devices", Nanobiotechnology Reports, 17(1), pp.24~38 (2022)
- Y. -B. Kim, "Sensor circuit design using carbon nanotube FET for artificial skin", J. Korea Soc. Ind. Inform. Syst., 19(3), pp.41~48 (2014)
- Y. Choi, "Design and analysis of a low-power ternary SRAM", Proc. of 2021 IEEE Int. Symp. Circuits Syst. (ISCAS), pp.1~4 (2021)
- J. Deng, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-Part I : Model of the intrinsic channel region", IEEE Trans. Electron Devices, 54(12), pp.3186~3194 (2007)
- J. Deng, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-Part II : Full device model and circuit performance benchmarking", IEEE Trans. Electron Devices, 54(12), pp.3195~3205 (2007)
- B. Srinivasu, "Low-power and high-performance ternary SRAM designs with application to CNT-FET technology", IEEE Trans. Nanotechnol., 20, pp.562~566 (2021)
- B. H. Calhoun, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS", IEEE J. Solid-State Circuits, 41(7), pp.1673~1679 (2006)