Area- and Energy-Efficient Ternary D Flip-Flop Design
1
조회
0
다운로드
0
인용
0
참고문헌
키워드
초록
In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequentiallogic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter withoutan additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancementof the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulationresults demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power–delay product improved by 36.35%. Theabove simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such asternary successive approximation register analog-to-digital converters.
Abstract
In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequentiallogic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter withoutan additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancementof the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulationresults demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power–delay product improved by 36.35%. Theabove simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such asternary successive approximation register analog-to-digital converters.
참고문헌 (13)
- P. Harpe, "Ultra Low Power Event-Driven Sensor Interfaces", Proc. of 2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI), pp.133~137 (2023)
- Y. Chae, "A Glimpse of the History of Analog ICs : A Tale of Amplifiers, Data Converters, and Sensor Interfaces", IEEE Solid-State Circuits Magazine, 15(3), pp.43~52 (2023)
- M. Ren, "Toward a Gas Sensor Interface Circuit-A Review", IEEE Sens. J., 22(19), pp.18253~18265 (2022)
- R. Wang, "A Review on the Key Optimization Techniques of SAR ADC Design", Proc. of 2021 International Conference on Electronic Information Engineering and Computer Science (EIECS), pp.951~957 (2021)
- H. Wang, "Low power consumption and low area capacitor array for 16-bit 1-MS", s SAR ADC, 2018, 1003~1006
- J. Guerber, "A 10-b Ternary SAR ADC With Quantization Time Information Utilization", IEEE J. Solid-State Circuits, 47(11), pp.2604~2613 (2012)
- Y. S. G. Reddy, "A low-power and areaefficient radix-3 SAR ADC", Proc. of 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.146~149 (2015)
- S. Kim, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", Proc. of 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), pp.37~42 (2019)
- Z. T. Sandhie, "Design of Ternary Master-Slave D-Flip Flop using MOSGNRFET", Proc. of 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp.554~557 (2020)
- M. H. Moaiyeri, "An efficient ternary serial adder based on carbon nanotube FETs", Eng. Sci. Technol. Int. J., 19(1), pp.271~278 (2016)
- N. H. E. Weste, "Principles of CMOS VLSI Design-A Circuits and Systems Perspective", pp.17~31 (2010), Addison-Wesley
- S. Kim, "A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits", IEEE Trans. Circuits. Syst. I Regul. Pap., 67(9), pp.3138~3151 (2020)
- D. Li, "Comparative analysis and study of metastability on high-performance flip-flops", Proc. of 2010 11th International Symposium on QualityElectronic Design, pp.853~860 (2010)