개선된 메모리 셀을 활용한 문턱전압 이하스태틱 램 어레이 설계
Design of Subthreshold SRAM Array utilizing Advanced Memory Cell
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초록
본 논문에서는 트랜지스터의 문턱전압 보다 낮은 초저전압 환경에서도 안정적으로 동작할 수 있는 8T SRAM에 대해 기술하였다. 제안한 메모리 셀은 대칭적인 8개의 트랜지스터로 구성되며, 셀 내부의 데이터 저장 래치는 열 방향의 보조라인을통해 제어된다. 읽기동작 시, 데이터 저장노드와 비트라인이 동적으로 분리되어 비트라인으로부터 교란을 받지 않는다. 또한,노이즈에 민감한 ‘0’-노드 전압상승이 낮아 dummy-read 안정도가 높다. 아울러, 제안한 셀은 쓰기능력을 높이기 위해boosting 전압을 사용한다. 상용화된 8T SRAM 셀과 비교했을 때, 제안한 셀의 dummy-read 마진과 쓰기마진이 0.4 V 전원전압에서 각각 65%, 3.7배 향상된 안정성을 보이며, 공정변화에 따른 안정도의 내성이 더 우수하다. 활용 예시를 위해 산업체에서 제공하는 180 nm CMOS 공정으로 SRAM 회로를 설계하여 그 동작 및 성능을 검증하였다.
Abstract
This paper suggests an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The memorycell consists of symmetric 8 transistors, in which the latch storing data is controlled by a column-wise assistline. Duringthe read, the data storage nodes are temporarily decoupled from the read path, thus eliminating the read disturbance. Additionally, the cell keeps the noise-vulnerable ‘low’ node close to the ground, thereby improving the dummy-readstability. In the write, the boosted wordline facilitates to change the contents of the memory bit. At 0.4 V supply, theadvanced 8T cell achieves 65% higher dummy-read stability and 3.7 times better write-ability compared to thecommercialized 8T cell. The proposed cell and circuit techniques have been verified in a 16-kbit SRAM array designedwith an industrial 180-nm low-power CMOS process.
참고문헌 (9)
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