탄소나노튜브 밀도를 고려한 CNTFET SRAM 디자인 방법에 관한 연구
A Study on the Circuit Design Method of CNTFET SRAM Considering Carbon Nanotube Density
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초록
CNTFET은 기존 반도체 소자의 성능을 약 13배 향상시킬 수 있어 큰 관심을 받아 왔지만, CNT를 일정하게 배치시키는공정의 미성숙으로 인해 상용화에 어려움을 겪어 왔다. 이러한 어려움을 극복하기 위해, 그동안 알려진 CNTFET 공정상 한계를 고려한 회로 디자인 방법이 점점 높은 관심을 받고 있다. SRAM은 마이크로프로세서를 구성하는 주요 요소로서 캐시메모리 안에 규칙적으로 그리고 반복적으로 배치되어 있어, SRAM 안의 CNT는 다른 회로 블록에 비해 보다 쉽게 그리고고밀도로 배치될 수 있는 장점이 있다. 이러한 장점을 활용하기 위해, 본 논문에서는 CNT 밀도를 고려한 SRAM 셀의 회로디자인 방법을 소개하고 그 성능 향상 정도를 HSPICE 시뮬레이션으로 검토하고자 한다. 시뮬레이션 결과, SRAM에CNTFET을 적용할 경우, gate width를 약 1.7배 줄일 수 있음을 발견하였으며, 동일한 gate width에서 CNT 밀도를 높였을경우, 읽기 속도 또한 약 2배 정도 향상될 수 있음을 알 수 있었다.
Abstract
Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performanceby about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition processof CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFETmanufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and isregularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily anddensely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuitdesign method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICEsimulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reducedby about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased inthe same gate width.
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