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신호 대 잡음비가 향상된 센서 신호 측정용 저 전력 SAR형 A/D 변환기

A Low Power SAR ADC with Enhanced SNDR for Sensor Application

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초록

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC(digital-to- analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12boperation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The pro-posed SAR ADC is designed with a 0.18 µm CMOS process. The simulation results show that the SNDR of the SAR ADC withoutthe noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dBimprovement in SNDR with this noise shaping technique. The power consumption is 73.8 µW and the FoM (figure-of-merit) is 5.2fJ/ conversion-step.

Abstract

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC(digital-to- analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12boperation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The pro-posed SAR ADC is designed with a 0.18 µm CMOS process. The simulation results show that the SNDR of the SAR ADC withoutthe noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dBimprovement in SNDR with this noise shaping technique. The power consumption is 73.8 µW and the FoM (figure-of-merit) is 5.2fJ/ conversion-step.

참고문헌 (10)

  1. 박창범, "생체 신호 측정용 저 잡음 저 전력 용량성 계측 증폭기", 센서학회지, 26(5), pp.342~347 (2017), 한국센서학회[DOI]
  2. 안경찬, "내장 필터를 갖는 15b 고해상도 혼합형 A", D 변환기, 2017, pp.26(5), 348~352[DOI]
  3. S.C. Rho, "Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System", IEIE Tran. on Smart Proc. & Comp., 4(3), pp.189~193 (2015)[DOI]
  4. S.M. Sohn, "ASIC design of DMPPT control for Photovoltaic Systems", Proc. of ISOCC 2013 (2013)
  5. J. Fredenburg, "A 90MS", s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC, 2012, 468~469
  6. J. Lin, "A 15.5dB, Wide Signal Swing, Dynamic Amplifier Using a Common-mode Voltage Detection Technique", IEEE ISCAS, pp.21~24 (2011)
  7. Sanyal. A, "An energy Efficient Low Frequency Dependence Switching Technique for SAR ADCs", IEEE Circuits and System: Express Briefs, 61(5), pp.294~298 (2014)[DOI]
  8. Y.S. Shu, "An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1kHz BW in 55 nm CMOS", IEEE JSSC, 51(12), pp.2928~2940 (2016)
  9. P.Harpe, "An oversampled 12", 14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1 dB SNDR, 2014, 194~195
  10. Chun-Cheng Liu, "A 0.46 mW 5 MHz- BW 79.7 dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter", IEEE ISSCC Dig. Tech. Papers, pp.466~467 (2017)

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