Design of a 10-bit SAR A/D converter with 2-bit/step and threshold configuring comparator
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In this paper, we designed an A/D converter that can be applied to a system that enables interface between human body and device such as touchpad. As devices become more sophisticated, higher operating speeds are required. Portable devices have been developed to minimize power consumption and miniaturize devices. The upper 5 bits are determined by digital code using a reference voltage variable comparator. The reference voltage variable comparator changes the offset by connecting the current path to the input pair, and the reference voltage is sequentially shifted according to the digital code of the upper 5 bits. The lower 5 bits change the reference voltage by the switching of the capacitor D/A converter to determine the digital code. This technique reduces the capacitance of the capacitor D/A converter, reduces dynamic power consumption, and reduces chip area. The clock double circuit reduces the period of the external clock by 2 times and increases the operation speed by 2 bits per step. The designed 10 - bit SAR A/D converter was fabricated with Magna chip 0.18μm CMOS 1Poly 6Metal process. Simulation results showed 56 power consumption and 9.5 bit ENOB at maximum sampling frequency of 10MHz for 1.8V supply voltage and 1 kHz sinusoidal input. The proposed SAR A/D converter with 7.73fJ/step FoM is expected to be applied to low power systems.
Abstract
In this paper, we designed an A/D converter that can be applied to a system that enables interface between human body and device such as touchpad. As devices become more sophisticated, higher operating speeds are required. Portable devices have been developed to minimize power consumption and miniaturize devices. The upper 5 bits are determined by digital code using a reference voltage variable comparator. The reference voltage variable comparator changes the offset by connecting the current path to the input pair, and the reference voltage is sequentially shifted according to the digital code of the upper 5 bits. The lower 5 bits change the reference voltage by the switching of the capacitor D/A converter to determine the digital code. This technique reduces the capacitance of the capacitor D/A converter, reduces dynamic power consumption, and reduces chip area. The clock double circuit reduces the period of the external clock by 2 times and increases the operation speed by 2 bits per step. The designed 10 - bit SAR A/D converter was fabricated with Magna chip 0.18μm CMOS 1Poly 6Metal process. Simulation results showed 56 power consumption and 9.5 bit ENOB at maximum sampling frequency of 10MHz for 1.8V supply voltage and 1 kHz sinusoidal input. The proposed SAR A/D converter with 7.73fJ/step FoM is expected to be applied to low power systems.
참고문헌 (9)
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