CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation
2
조회
0
다운로드
5
인용
0
참고문헌
키워드
초록
A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposedCMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with 394 (H) × 250 (V) pixels, scanners, bias circuits, and col-umn parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process
Abstract
A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposedCMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with 394 (H) × 250 (V) pixels, scanners, bias circuits, and col-umn parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process
참고문헌 (15)
- E. R. Fossum, "CMOS image sensors: electronic camera-on-a-chip", IEEE Trans. Electron Devices, 44(10), pp.1689~1698 (1997)
- M. Bigas, "Review of CMOS image sensors", Microelectronics J, 37(5), pp.433~451 (2006)
- H. P. Wong, "CMOS Image sensors - Recent Advances and Device Scaling Considerations", Int. Electron Devices Meet. (IEDM), pp.201~204 (1997)
- S. Kleinfelder, "A 10000frames", s CMOS digital pixel sensor, 2001, pp.36(12), 2049~2059
- J. Choi, "Review of low power image sensors for alwayson imaging", Int. SoC Des. Conf.: Smart SoC for Intell. Things, pp.11~12 (2016)
- N. Kawai, "Measurement of low-noise column readout circuits for CMOS image sensors", IEEE Trans. Electron Devices, 53(7), pp.1737~1739 (2006)
- W. Zhang, "A high gain N-Well", Gate tied PMOSFET image sensor fabricated from a standard CMOS process, 2001, pp.48(6), 1097~1102
- F. Yang, "Oversampled noisy binary image sensor", Proc. of IEEE Conf. on Acoust., Speech Signal Process, pp.2060~2064 (2013)
- B. S. Choi, "Complementary Metal Oxide Semiconductor Image Sensor Using Gate", Body-tied P-channel Metal Oxide Semiconductor Field Effect Transistor-type Photodetector for High-speed Binary Operation, 2018, pp.30(1), 129~134
- S. H. Seo, "Optical Characteristics of an N-Well", Gate-Tied PMOSFET-type Photodetector with Built-in Transfer Gate for CMOS Image Sensor, 2007, pp.19(7), 435~444
- C. S. Hong, "On-chip binary image processing with CMOS image sensor", Proc. SPIE, 4669, pp.125~136 (2002)
- A. Rabiei, "A New Ultra Low Power High Speed Dynamic Comparator", Iran. Conf. Electr. Eng, pp.1266~1270 (2015)
- A. D. Shinde, "Low Power, Area Efficient Dynamic Comparator with Reduced Activity Factor", Int. Conf. Inf., Commun., Instrum. and Control (2017)
- M. Jin, "Design of a High-speed CMOS Image Sensor with an Intelligent Digital Correlated Double Sampling and a Symmetrical 3-Input Comparator", Second Int. Conf. on Adv. Sens., Actuators Metering Sens, pp.1~4 (2017)
- J. H. Park, "A 142dB dynamic range CMOS image sensor with multiple exposure time signals", IEEE Asian Solid-State Circuits Conf, pp.85~88 (2005)