Simulation of High-Speed and Low-Power CMOS Binary Image Sensor Based on Gate/Body-Tied PMOSFET-Type Photodetector Using Double-Tail Comparator
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초록
In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT)p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeedand low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a bodythat amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltageand returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superiorover those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the outputvoltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low powerconsumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard0.18 µm CMOS process.
Abstract
In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT)p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for highspeedand low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a bodythat amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltageand returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superiorover those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the outputvoltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low powerconsumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard0.18 µm CMOS process.
참고문헌 (17)
- E. R. Fossum, "CMOS Image Sensors : Electronic Camera-On-A-Chip", IEEE Trans. Electron Devices, 44(10), pp.1689~1698 (1997)
- S. Mehta, "CCD or CMOS Image sensor for photography", 2015 Int. Conf. Commun. Signal Process. ICCSP 2015, pp.291~294 (2015)
- B. S. Carlson, "Comparison of Modern CCD and CMOS Image Sensor Technologies and Systems for Low Resolution Imaging", Proc. IEEE Sens, 1(1), pp.171~176 (2002)
- M. Bigas, "Review of CMOS image sensors", Microelectron. J, 37(5), pp.433~451 (2006)
- B. Luo, "Research of noise suppression for CMOS image sensor", 2010 Int. Conf. Meas. Technol. Mechatron. Autom. ICMTMA 2010, 2, pp.1100~1103 (2010)
- N. Tanaka, "A novel bipolar imaging device with self noise reduction capability", IEEE Trans. Electron Devices, 36(1), pp.31~38 (1989)
- A. Rochas, "Low-noise silicon avalanche photodiodes fabricated in conventional CMOS technologies", IEEE Trans. Electron Devices, 49(3), pp.387~394 (2002)
- W. Zhang, "A high gain N-Well", Gate tied PMOSFET image sensor fabricated from a standard CMOS process, 2001, pp.48(6), 1097~1102
- H. H. Lee, "Highly sensitive gate", body-tied metaloxide-semiconductor field-effect transistor-type photodetector with wavelength-selective metal grid structure using standard complementary metal-oxide-semiconductor technology, 2015, pp.27(1), 135~142
- B. S. Choi, "Complementary metal oxide semiconductor image sensor using gate", body-tied P-channel metal oxide semiconductor field effect transistor-type photodetector for high-speed binary operation, 2018, pp.30(1), 129~134
- 최병수, "High-Speed CMOS Binary Image Sensor with Gate", Body-Tied PMOSFET-Type Photodetector, 2014, pp.23(5), 332~336[DOI]
- 이준우, "CMOS Binary Image Sensor with Gate", Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation, 2018, pp.27(6), 362~367[DOI]
- B. Zhang, "Reconfigurable processor for binary image processing", IEEE Trans. Circuits Syst. Video Technol, 23(5), pp.823~831 (2013)
- S. Masoodian, "A 2. 5 pJ", b Binary Image Sensor as a Pathfinder for Quanta Image Sensors, 2016, pp.63(1), 100~105
- D. Schinkel, "A double-tail latch-type voltage sense amplifier with 18ps setup+hold time", Dig. Tech. Pap. -IEEE Int. Solid-State Circuits Conf, pp.314~316 (2007)
- S. Chaudhari, "Design of efficient double tail comparator for low power", 2015 Int. Conf. Commun. Signal Process. ICCSP 2015, pp.1782~1785 (2015)
- S. Mashhadi, "Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator", IEEE Trans. VLSI Syst, 22(2), pp.343~352 (2014)