New Multiplication Architecture for DSP Applications
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초록
he modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.
Abstract
he modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.
참고문헌 (21)
- Walt Kester, "Mixed-Signal and DSP Design Techniques" (2003), Analog Devices
- Amitabha, "Triple-Base Number Digital Signal and Numerical Processing System", US Patent, 24 (2008)
- Kacem, R, "Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing", The 2nd International Conference on Signals, pp.1~6 (2008), Circuits and Systems
- Vassil S. Dimitrov, "Theory and Applications of the Double-Base Number System", IEEE Tran. on Computers, 48, pp.1098~1106 (1999)
- Vassil S. Dimitrov, "A New Number Representation with Applications", IEEE Circuits and Systems Magazine (2003)
- Roberto Muscedere, "Efficient Techniques for Binary to Multidigit Multidimensional Logarithmic Number System Conversion Using Range Addressable Look-Up Tables", IEEE Tran. on Computers, 54(3), pp.257~271 (2005)
- Sheng-Chien Huang, "A 32-bit Logarithmic Number System Processor", Journal of VLSI Signal Processing, 14, pp.311~319 (1996)
- Suganth Paul, "A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations", IEEE Tran. on VLSI, 17, pp.269~277 (2009)
- K. Johansson, "Implementation of elementary functions for logarithmic number systems", IET Comput. Digit. Tech, 2, pp.295~304 (2008)
- Tso-Bing Juang, "A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications", IEEE Tran. on Circuit and Systems, 56, pp.931~935 (2009)
- Huey Ling, "High-Speed Binary Adder", IBM Journal of Research and Development, 5(3) (1981)
- Mustafa GOK, "A Novel IEEE Rounding Algorithm for High-speed Floating-point Multipliers", The VLSI journal, pp.549~560 (2007)
- Bhaskar D. Rao, "Floating-point Arithmetic and Digital filter", IEEE Tran. on Signal Processing, 40, pp.85~95 (1992)
- Christian Piguet, "Low-Power CMOS Circuit: Technology, Logic Design and CAD tools" (2006), Taylor & Fracis
- 김종수, "The Conversion Algorithm between Double-Base Number System and Floating-Point Number System applied for FIR filter", ITC-CSCC 2009, pp.1458~1461 (2009), IEEK, IEICE,
- Minh Son Nguyen, "Design and Implementation of Flash ADC and DBNS FIR filter integrated on DSP System", ISOCC’09, 1(1), pp.430~435 (2009)
- Nguyen-Minh Son, "Algorithm and Design of Double-base Log Encoder for Flash A", D Converters, 2009, pp.10(4), 289~293[DOI]
- D Converter, "Design Method and Automation of Comparator Generation for Flash A", pp.2002, Daegyu Lee
- Jaehyun Lim, "Low Power Flash A", D Converter with TIQ Comparators for Multi-Standard Mobile Applications, 2009, pp.4, 1447~1452
- Daegyu Lee, "Fat Tree Encoder Design for Ultra-High Speed Flash A", D Converters, 2002, pp.2, 87~90
- Jincheol Yoo, "A TIQ Based CMOS Flash A", D Converter for SoC Applications, The Pennsylvania State University, pp.Comp. Sci. and Eng, 2003