Hardware Implementation of -times Fast Hybrid Polynomial Basis Multiplier over GF(2m)
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Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a hardware implementation of -times fast hybrid finite field multiplier is presented. The proposed multiplier is used for polynomial basis of finite fields . The proposed architecture is -times faster than bit-serial architectures but with lower area complexity than bit-parallel ones, where the value for , , can be arbitrarily selected by the designer to set the tradeoff between area and speed. In this multiplier, a field element of -bit length is subdivided into several parts to speed up the multiplication operation. In every clock cycle, the multiplication of -bit sub-word and an -bit multiplicand produces one -bit product. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. This makes the proposed multipliers suitable for applications where the value of is large but space is of concern, e.g., resource constrained cryptographic systems. In addition, the proposed architecture is highly regular, simple, expandable and therefore, well-suited for VLSI implementation.
Abstract
Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a hardware implementation of -times fast hybrid finite field multiplier is presented. The proposed multiplier is used for polynomial basis of finite fields . The proposed architecture is -times faster than bit-serial architectures but with lower area complexity than bit-parallel ones, where the value for , , can be arbitrarily selected by the designer to set the tradeoff between area and speed. In this multiplier, a field element of -bit length is subdivided into several parts to speed up the multiplication operation. In every clock cycle, the multiplication of -bit sub-word and an -bit multiplicand produces one -bit product. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. This makes the proposed multipliers suitable for applications where the value of is large but space is of concern, e.g., resource constrained cryptographic systems. In addition, the proposed architecture is highly regular, simple, expandable and therefore, well-suited for VLSI implementation.
참고문헌 (12)
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