Design of a Reconfigurable Multiplier with Variable-Precision
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Multipliers remain as a key computational element in numerous high-performance digital systems determining the overall performance of the system. In this paper, we introduce a variable-precision reconfigurable multiplier by employing vertical and horizontal control signals and compare the performance against the conventional fixed-precision multiplier in terms of power dissipation and propagation delay. The proposed multiplier has enhanced performance in terms of power reduction by 64%, area reduction by 48% and furthermore 60% improvement in propagation delay. The reconfigurable multiplier was implemented under Magnachip / SK Hynix 0.35um process and a 3.3V supply voltage. Xilinx FPGA Basys3(xc7a35tcpg-236L) board was used to verify the function of parallel operation and the performance of the implemented multiplier. As a result, the proposed multiplier shows 22.5ns a worst-case propagation delay.
Abstract
Multipliers remain as a key computational element in numerous high-performance digital systems determining the overall performance of the system. In this paper, we introduce a variable-precision reconfigurable multiplier by employing vertical and horizontal control signals and compare the performance against the conventional fixed-precision multiplier in terms of power dissipation and propagation delay. The proposed multiplier has enhanced performance in terms of power reduction by 64%, area reduction by 48% and furthermore 60% improvement in propagation delay. The reconfigurable multiplier was implemented under Magnachip / SK Hynix 0.35um process and a 3.3V supply voltage. Xilinx FPGA Basys3(xc7a35tcpg-236L) board was used to verify the function of parallel operation and the performance of the implemented multiplier. As a result, the proposed multiplier shows 22.5ns a worst-case propagation delay.
참고문헌 (7)
- D. J. M. Moss, "A Two-Speed, Radix-4, Serial-Parallel Multiplier", IEEE Transactions on Very Large Scale Integration(VLSI)System, 27(4), pp.769~777 (2018)
- Y. Harata, "A high-speed multiplier using a redundant binary adder tree", IEEE journal of Solid-State Circuits, 22(1), pp.28~34 (1987)
- P. Kitsos, "An efficient reconfigurable multiplier architecture for Galois filed GF", Microelectronics journal, 34(10), pp.975~980 (2003)
- SJ. Lee, "Memristor – CMOS reconfigurable multiplier architecture", Cellular Nanoscale Networks and their Applications(CNNA), 2014 14th International Workshop on, pp.1~2 (2014)
- R. Gnanasekran, "A fast serial-parallel binary multiplier", IEEE transactions on computers, 8, pp.741~744 (1985)
- S. S. Mahant-Shetti, "High performance low power array multiplier using temporal tiling", IEEE Transactions on Very Large Scale Integration(VLSI)system, 7(1), pp.121~124 (1999)
- H J. Kang, "FIR filter synthesis algorithms for minimizing the delay and the number of adders", IEEE Transactions on Circuits and Systems ǁ: Analog and Digital Signal Processing, 48(8), pp.770~777 (2001)