Application of Constraint Algorithm for High Speed A/D Converters
0
조회
0
다운로드
1
인용
0
참고문헌
키워드
초록
In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with 0.18 CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.
Abstract
In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with 0.18 CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.
참고문헌 (16)
- Vassil S. Dimitrov, "A New Number Representation with applications", IEEE Circuits and Systems Magazine (2003)
- Vassil S. Dimitrov, "Theory and applications of the double-base number system", IEEE Transactions on Computers, 48, pp.1098~1106 (1999)
- G. Gilbert, "Multipath greedy algorithm for canonical representation of numbers in the double base number system", IEEE-NEWCAS Conference, pp.39~42 (2005)
- More on Converting Numbers to the Double-Base Number System, "V. Berthe", Research Report LIRMM - 0403 1, ~ (2004)
- Y. Ibrahim, "DBNS addition using cellular neural networks", IEEE International Symposium on Circuits and Systems, 통권 : 4, pp.3914~3917 (2005)
- M. Pankaala, "Implementation alternatives of a DBNS adder", 9th International Workshop on Cellular Neural Networks and Their Applications, pp.138~141 (2005)
- Kriangyut Wangjitman, "Addition transducer for double base number system", ISCIT’06, pp.994~999 (2009)
- Reinhard Diestel, "Graph Theory" (2000), Springer-Verlag
- Jincheol Yoo, "''A TIQ Based CMOS Flash A", D Converter for SoC Applications, The Pennsylvania State University, pp.Department of Computer Science and Engineering, 2003
- Daegyu Lee, "Fat Tree Encoder design for Ultra-high speed Flash A", D Converters, 2002, pp.통권 : 2, 87~90
- Jincheol Yoo, "A Power and Resolution Adaptive Flash Analog-to-Digital Converter", ISLPED'02, pp.233~236 (2002)
- Daegyu Lee, "Design Method and Automation of Comparator Generation for Flash A", D Converter, 2002, 138~142
- D.P. Dimitrov, "8-bit semi-Flash A", D Converter, 2006, 171~174
- Chia-Chun Tsai, "New Power Saving Design Method for CMOS Flash ADC", The 47th IEEE International Midwest Symposium on Circuit and System, pp.Ⅲ-371~Ⅲ-374 (2004)
- Neil H.E. Weste, "CMOS VLSI design-A circuits and systems perspective", 3rd edition" (2004), Addison-Wesley
- Jongsoo Kim, "A New Flash A", D Converter Adopting Double Base Number System, 2008, pp.9(1), 54~61