3차원 실장을 위한 TSV의 Cu 전해도금 및 로우알파 솔더 범핑
Cu Electroplating and Low Alpha Solder Bumping on TSV for 3-D Packaging
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초록
Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.
Abstract
Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.
참고문헌 (27)
- J. H. Jun, "A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging", Materials Transactions, 51(10), pp.1887~ (2010)
- S. Kumar, "High-Speed Shear Test for Low Alpha Sn-1.0%Ag-0.5%Cu (SAC-105) Solder Ball of Sub-100-μm Dimension for Wafer Level Packaging", IEEE Trans. Compon., Packag, Manuf. Technol, 3(3), pp.441~ (2013)
- S. J. Hong, "Filling via hole in Si-wafer for 3 Dimensional Packaging", Proc. The Korean Welding and Joining Society (KWS), pp.227~ (2006)
- 유선중, "BGA 현상 공정 용 수직 습식 장비 개발 및 공정 특성 평가", 마이크로전자 및 패키징학회지, 16(3), pp.45~51 (2009), 한국마이크로전자및패키징학회
- S. P. Shen, "Copper seed layer repair using an electroplating process for through silicon via metallization", Microelectronic Engineering, 105, pp.25~ (2013)
- T. Kenji, "Current status of research and development for three-dimensional chip stack technology", J. Appl. Phys, 40, pp.3032~ (2001)
- R. Lee, "3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling", Proc. 55th Elec. Pack. Tech. Conf. (EPTC), pp.795~ (2005)
- 김양도, "실리콘 관통형 Via(TSV)의 Seed Layer 증착 및 Via Filling 특성", 한국재료학회지, 23(10), pp.550~554 (2013), 한국재료학회
- B. H. Kim, "Cantilevert-type microelectromechanical systems probe card with through-wafer interconnects for fine pitch and highspeed testing", J. Applied Physics, 43(6B), pp.3877~ (2004)
- F. Inoue, "Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias", Electrochimica Acta, 100(30), pp.203~ (2013)
- M. Knaut, "Atomic layer deposition for high aspect ratio through silicon vias", Microelec. Eng, 107, pp.80~ (2013)
- S. Yamamoto, "Si through-hole interconnections filled with Au-Sn solder by molten metal suction method", Proc. 16th IEEE International Conference, pp.642~ (2003)
- C. Lee, "Formation of 100-μm-deep Vertical Pores in Si Wafers by Wet Etching and Cu Electrodeposition", J. Electrochem. Soc, 156(12), pp.D543~ (2009)
- T. Hayashi, "High-Speed Through Silicon Via(TSV) Filling Using Diallylamine Additive", J. Electrochem. Soc, 158(12), pp.715~ (2011)
- H. Y. Li, "Fast Electroplating TSV Process Development for the Via- Last Approach", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, pp.777~ (2010), IEEE Components
- H. Banha, "High speed TSV filling", Proc. 24th Micro Electron. Sympo, pp.53~ (2015)
- A. Pohjoranta, "A Method for Microvia-Fill Process Modeling in a Cu Plating System with Additives", J. Electrochem. Soc, 154(10), pp.D502~ (2007)
- 김인락, "3차원 Si칩 실장을 위한 경사벽 TSV의 Cu 고속 충전", 대한금속·재료학회지, 49(5), pp.388~394 (2011), 대한금속·재료학회
- 김인락, "3차원 실장용 TSV의 펄스전류 파형을 이용한 고속 Cu도금 충전", 대한금속·재료학회지, 48(7), pp.667~673 (2010), 대한금속·재료학회
- S. C. Hong, "Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking", Microelectronics Reliability, 51, pp.2228~ (2011)
- 홍성철, "3차원 Si칩 실장을 위한 효과적인 Cu 충전 방법", 대한금속·재료학회지, 50(2), pp.152~158 (2012), 대한금속·재료학회
- 이순재, "Wafer 레벨에서의 위치에 따른 TSV의 Cu 충전거동", 마이크로전자 및 패키징학회지, 21(4), pp.91~96 (2014), 한국마이크로전자및패키징학회[DOI]
- P. Dixit, "Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating", J. Miceomech. Microeng, 17(5), pp.1078~ (2007)
- S. J. Hong, "Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging", IEEE Transactions on Advanced Packaging, 33(4), pp.912~ (2010)
- S. Kumar, "Wetting behavior and elastic properties of low alpha SAC105 and pure Sn solder", J. Mater. Sci.: Mater. Electron, 24(6), pp.1748~ (2012)
- J. F. Ziegler, "The effect of sea level cosmic rays on electronic devices", J. Appl. Phys, 52(6), pp.4305~ (1981)
- D. H. Jung, "Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping", J. Mater. Eng. and Perf, 24(3), pp.1107~ (2015)