Cu-SiO2 하이브리드 본딩
Cu-SiO2 Hybrid Bonding
0
조회
0
다운로드
9
인용
0
참고문헌
키워드
초록
As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to finepitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO2 hybrid bonding.
Abstract
As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to finepitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO2 hybrid bonding.
참고문헌 (38)
- R. S. List, "3D wafer stacking technology", Proc. Advanced Metallization Conference (2002)
- J. Q. Lu, "3D Integration Using Adhesive, Metal, and Metal", Adhesive as Wafer Bonding Interfaces, 2008, pp.1112, ~
- C. Ko, "Low temperature bonding technology for 3D integration", Microelectron. Reliab, 52, pp.302~ (2012)
- A. K. Panigrahy, "Low Temperature Cu–Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review", J. Electron. Packaging, 140(1), pp.010801~ (2018)
- K. N. Chen, "Abnormal Contact Resistance Reduction of Bonded Copper Interconnects in Three-Dimensional Integration During Current Stressing", Appl. Phys. Lett, 86(1), pp.011903~ (2005)
- H. Park, "Nitrogen passivation formation on Cu surface by Ar–N2 plasma for Cu-to-Cu wafer stacking application", Microsyst. Technol, 25, pp.3847~ (2019)
- R. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs", Proc. IEEE, 94(6), pp.1214~ (2006)
- H. S. Park, "Two-Step Plasma Treatment on Copper Surface for Low Temperature Cu Thermo-Compression Bonding", IEEE Trnas. Comp. Packag. Manuf. Technol, 10(2), pp.332~ (2019)
- M. Park, "Argon plasma treatment on Cu surface for Cu bonding in 3Dintegration and their characteristics", Appl. Surf. Sci, 324, pp.168~ (2015)
- H. Takagi, "Surface activated bonding of Silicon wafers at room temperature", Appl. Phys. Lett, 68(16), pp.2222~ (1996)
- E. J. Jang, "Effect of Wet Pretreatment on Interfacial Adhesion Energy of Cu–Cu Thermocompression Bond for 3D IC Packages", J. Electron. Mater, 38, pp.2449~ (2009)
- A. Huffman, "Fabrication and Characterization of Metal-to-Metal Interconnect Structures for 3-D Integration", J. Instrum, 4(3), pp.P03006~ (2009)
- K. N. Chen, "Copper Bonded Layers Analysis and Effects of Copper Surface Conditions on Bonding Quality for Three-Dimensional Integration", J. Electron. Mater, 34(12), pp.1464~ (2005)
- C. S. Tan, "Cu-Cu Diffusion Bonding Enhancement at Low Temperature by Surface Passivation Using Self-assembled Monolayer of Alkane-thiol", Appl. Phys. Lett, 95(19), pp.192108~ (2009)
- Y. P. Huang, "Novel Cu-to-Cu Bonding With Ti Passivation at 180oC in 3-D Integration", IEEE Electron. Dev. Lett, 34(12), pp.1551~ (2013)
- Z. Liu, "Modified pulse laser deposition of Ag nanostructure as intermediate for low temperature Cu–Cu bonding", Appl. Surf. Sci, 445, pp.16~ (2018)
- H. Oprins, "Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu", Dielectric Wafer-to-Wafer Bonding, 2017, pp.139(1), 011008~
- I. Jani, "Characterization of Fine Pitch Hybrid Bonding Pads using Electrical Misalignment Test Vehicle", Proc. 69th Electronic Components and Technology Conference(ECTC), pp.1926~ (2019), IEEE
- Y. Beilliard, "Thermomechanical finite element modeling of Cu-SiO2 direct hybrid bonding with a dishing effect on Cu surfaces", Int. J. Solids Struct, 117, pp.208~ (2017)
- G. Gao, "Low Temperature Cu Interconnect with Chip to Wafer Hybrid Bonding", Proc. 69th Electronic Components and Technology Conference(ECTC), pp.628~ (2019), IEEE
- P. Enquist, "Low cost of ownership scalable copper Direct Bond Interconnect 3D IC technology for three-dimensional integrated circuit applications", IEEE International Conference on 3D System Integration (3DIC) (2009)
- G. Gao, "Chip to Wafer Hybrid Bonding with Cu Interconnect: High Volume Manufacturing Process Compatibility Study", International Wafer-Level Packaging Conference (IWLPC) (2019)
- R. He, "Combined Surface Activated Bonding Technique for Hydrophilic SiO2-SiO2and Cu-Cu Bonding", ECS Transactions, 75(9), pp.117~ (2016)
- T. Wlanis, "Cu-SiO2 hybrid bonding simulation including surface roughness and viscoplastic material modeling: A critical comparison of 2D and 3D modeling approach", Microelectron. Reliab, 86, pp.1~ (2018)
- K. N. Chen, "Demonstration and Electrical Performance Investigation of Wafer-Level Cu Oxide Hybrid Bonding Schemes", IEEE Electron Device Lett, 32(8), pp.1119~ (2011)
- S. Kim, "Cu Microstructure of High Density Cu Hybrid Bonding Interconnection", Proc. 69th Electronic Components and Technology Conference (ECTC), pp.636~ (2019), IEEE
- "Samsung Galaxy S7 Edge Teardown" (2016)[URL]
- P. Morrow, "Wafer-Level 3D Interconnects Via Cu Bonding", Proc. Advanced Metallization Conference (2004)
- P. R. Morrow, "Three-Dimensional Wafer Stacking Via Cu–Cu Bonding Integrated With 65-nm Strained-Si", Low-k CMOS Technology, 2006, pp.27(5), 335~
- Z. J. Hu, "Cu CMP process development and characterization of Cu dishing with 1.8 μm Cu pad and 3.6 μm pitch in Cu", SiO2 hybrid bonding, 2019, pp.58(SH), SHHC01~
- L. Di Cioccio, "An Overview of Patterned Metal", Dielectric Surface Bonding: Mechanism, Alignment and Characterization, 2011, pp.158(6), 81~
- C. M. Liu, "Low-temperature direct copper-to-copper bonding enabled by creep on highly(1 1 1)-oriented Cu surfaces", Scr. Mater, 78–79, pp.65~ (2014)
- C. M. Liu1, "Low-temperature direct copper-to-copper bonding enabled by creep on (111)surfaces of nanotwinned Cu", Sci. Rep, 5, pp.9734~ (2015)
- J. Y. Juang, "Copper-to-copper direct bonding on highly (111)-oriented nanotwinned copper in no-vacuum ambient", Sci. Rep, 8, pp.13910~ (2018)
- 박해성, "Ar-N2 플라즈마가 Cu 표면에 미치는 구조적 특성 분석", 마이크로전자 및 패키징학회지, 25(4), pp.75~81 (2018), 한국마이크로전자및패키징학회
- R. Gonzalez-Arrabal R, "Thermal stability of copper nitride thin films: The role of nitrogen migration", J. Appl, Phys, 107(10), pp.103513~ (2010)
- R. He, "Combined Surface Activated Bonding Technique for Low-Temperature Cu", Dielectric Hybrid Bonding, 2016, pp.5(7), 419~
- 김재원, "4-point bending test system을 이용한 Cu-Cu 열 압착 접합 특성 평가", 마이크로전자 및 패키징학회지, 18(4), pp.11~18 (2011), 한국마이크로전자및패키징학회