본문 바로가기
KERD
논문KCI 등재

3D 적층 IC를 위한 웨이퍼 레벨 본딩 기술

Wafer Level Bonding Technology for 3D Stacked IC

김은경|김성동|조영학
한국마이크로전자및패키징학회 (The Microelectronics And Packaging Society)|2013.03|마이크로전자 및 패키징학회지 (Jornal of the Microelectronics and Packaging Society)|제20권 제1호|pp. 7-13|DOI http://dx.doi.org/10.6117/kmeps.2013.20.1.007

0

조회

0

다운로드

14

인용

0

참고문헌

키워드

bonding3D ICwafer level stackingthermo-compression
주제분류재료공학

초록

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

Abstract

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

참고문헌 (31)

  1. Hongsik Park, "High-density integration of carbon nanotubes via chemical self-assembly", Nature Nanotechnology, 7, pp.787~791 (2012)
  3. Kim, Kinam, "Future silicon technology", Proceedings of the European Solid-State Device Research Conference (ESSDERC) (2012)
  4. Kye, Jongwook, "A Brief Overview of Lithographic Advancements in the Last Decade with a Focus on Double Patterning, In Recent Topics on Modeling of Semiconductor Processes, Devices, and Circuits", pp.3~ (2011), Bentham Science Publishers
  5. E. Kim, "Yield challenges in wafer stacking technology", Microelectron. Reliab, 48, pp.1102~1105 (2008)
  6. Reda, S, "Maximizing the functional yield of wafer-to-wafer 3-D integration", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), pp.1357~1362 (2009)
  7. Stengl, R, "A model for the silicon wafer bonding process", Japanese Journal of Applied Physics, 28(1), pp.1735~1741 (1989)
  8. R. Jansen, "The spin-valve transistor: fabrication, characterization and physics", J. Appl. Phys, 89(11), pp.7431~7436 (2001)
  9. T. Shimatsu, "Atomic diffusion bonding of wafers with thin nanocrystalline metal films", J. Vac. Sci. Technol. B, 28, pp.706~714 (2010)
  10. Suga T, "Low temperature bonding for 3D integration-A review of the surface activated bonding (SAB)", 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D), pp.7~10 (2012)
  11. Ko, Cheng-Ta, "Low temperature bonding technology for 3D integration", Microelectronics Reliability, 52, pp.302~311 (2012)
  12. Kim, T. H, "Room temperature Cu-Cu direct bonding using surface activated bonding method", Journal of Vacuum Science & Technology A, 21(2), pp.449~453 (2003)
  13. Shigetou, A, "Direct bonding of CMPCu films by surface activated bonding (SAB) method", Journal of Materials Science, 40(12), pp.3149~3154 (2005)
  14. Chen, K. N, "Morphology and bond strength of copper wafer bonding", Electrochemical and Solid-State Letters, 7(1), pp.G14~G16 (2004)
  15. Jang, E. J, "Effect of wet pretreatment on interfacial adhesion energy of Cu-Cu thermocompression bond for 3D IC packages", Journal of Electronic Materials, 38(12), pp.2449~2454 (2009)
  16. Gaudin, G., "Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment", 2010 IEEE International 3D Systems Integration Conference (3DIC), pp.1~4 (2010)
  17. Tang, Y. S., "Wafer-level Cu- Cu bonding technology", Microelectronics Reliability, 52(2), pp.312~320 (2012)
  18. Radu, I., "Recent Developments of Cu- Cu non-thermo compression bonding for wafer-to-wafer 3D stacking", 2010 IEEE International 3D Systems Integration Conference (3DIC), pp.1~6 (2010)
  19. Gueguen, P, "Copper direct bonding for 3D integration", International Interconnect Technology Conference 2008, pp.61~63 (2008)
  20. Gueguen, P., "Copper Direct-Bonding Characterization and Its Interests for 3D Integration", Journal of The Electrochemical Society, 156(10), pp.H772~H776 (2009)
  21. Frank Fournel, "presentation at Atelier Thématique du GDR MECANO", ~ (2011)
  22. Lee, B, "A Study on the Breakdown Mechanism of an Electroless- Plated Ni (P) Diffusion Barrier for Cu", Sn, Journal of Electronic Materials, pp.2011[DOI]
  23. Ko, C. T, "Wafer-to-wafer hybrid bonding technology for 3D IC", 3rd Electronic System-Integration Technology Conference (ESTC), pp.1~5 (2010)
  24. Reed, J. D, "Low temperature bonding of high density large area array interconnects for 3D integration", 43rd IMAPS Conference, 2 (2010)
  25. Jourdain, A, "Simultaneous Cu-Cu and compliant dielectric bonding for 3D stacking of ICs", IEEE International Interconnect Technology Conference, pp.207~209 (2007)
  26. Lu, J. Q, "3D Integration using adhesive, metal, and metal", adhesive as wafer bonding interfaces, 2008, pp.1112(1), ~
  27. Enquist, P., "High density direct bond interconnect (DBI) technology for three dimensional integrated circuit applications", MRS Proceedings, 970(1) (2006)
  28. Enquist, P, "Scalability and Low Cost of Ownership Advantages of Direct Bond Interconnect (DBI®) as Drivers for Volume Commercialization of 3-D Integration Architectures and Applications", MRS Proceedings, 1112(33) (2009)
  30. 강성근, "Fabrication and Challenges of Cu-to-Cu Wafer Bonding", 마이크로전자 및 패키징학회지, 19(2), pp.29~33 (2012), 한국마이크로전자및패키징학회[DOI]
  31. 김은솔, "웨이퍼 레벨 3D Integration을 위한 Ti", Cu CMP 공정 연구, 2012, pp.19(3), 37~41[DOI]

관련 논문AI추천

Optimal pressure and temperature for Cu–Cu direct bonding in three-dimensional packaging of stacked integrated circuits염승현, 현준원한국표면공학회 · 한국표면공학회지2023 · 제56권 제3호Fabrication and Challenges of Cu-to-Cu Wafer Bonding강성근, 김성동, 김수형, 김은솔, 이지은, 임나은, 김사라은경한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2012 · 제19권 제2호Cu-SiO2 하이브리드 본딩김은경, 박해성, 서한결한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2020 · 제27권 제1호첨단 반도체 패키징을 위한 저온 Hybrid Cu Bonding 연구 동향노은채, 백송연, 윤정원, 이동복, 한다경한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2025 · 제32권 제2호Cu 두께에 따른 Cu-Cu 열 압착 웨이퍼 접합부의 접합 특성 평가김재원, 박영배, 이학주, 정명혁, 현승민, Bioh Kim, Erkan Carmak, Thorsten Matthias한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2010 · 제17권 제4호Cu-to-Cu 웨이퍼 적층을 위한 Cu CMP 특성 분석김성동, 김은경, 송인협, 이민재한국마이크로전자및패키징학회 · 마이크로전자 및 패키징학회지2013 · 제20권 제4호

이 간행물의 다른 논문 (6건)

Wafer-to-Wafer Integration을 위한 생산수율 챌린지에 대한 연구김은경pp. 1-50.5 vol% TiO2 나노분말을 분산시킨 n형 Bi2(Te0.9Se0.1)3 가압소결체의 열전특성오태성, 박동현pp. 15-19잔류응력으로 인한 패키지 기판 굽힘 변형량 예측김민성, 김택수, 최혜선, 김철규pp. 21-26Deposition Optimization and Property Characterization of Copper-Oxide Thin Films Prepared by Reactive Sputtering김영환, 배승묵, 황진하, 유일환pp. 27-31저온수열합성방법에 의해 성장한 ZnO 나노로드의 전구체 몰농도 변화에 따른 특성 연구문대화, 하준석pp. 33-37
원문 보기